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Acacia Semiconductor to Present at ISSCC 2006
CAPARICA, Portugal -- January 30, 2006 — Acacia Semiconductor announced today that co-founder Dr. Goes et. al. will be presenting a paper at the IEEE International Solid-State Circuits Conference, to be held in February 5-9th, 2006, in San Francisco, USA. The paper entitled “A 0.9V Sigma-Delta Modulator with 80dB SNDR and 83dB DR using a Single-Phase Technique” is part of the Oversampling ADCs Session 3.7. The paper is the result of a joint R&D initiative with Universidade Nova de Lisboa and presents new design techniques that simplify the design, reduce die area and improve the energy-efficiency of sigma-delta ADCs, all fundamental requirements demanded by a growing number of portable systems spanning from voice to biomedical applications. “The ISSCC is the most important forum for semiconductor design innovation in the world and we are delighted to see our design team recognized as a leader in analog design”, said Bernardo Henriques, CEO of Acacia Semiconductor. The modulator is a second-order switched capacitor sigma-delta modulator featuring a 5.128MHz clock rate, an over-sampling rate of 256, a typical input differential voltage range of 1Vp-p and an input signal bandwidth of 10kHz. The circuit was fabricated in a 0.18µm CMOS process, occupies an ultra-small core die area of 0.06mm2, and was first-time-right. Silicon characterization results show an SNR of 82dB, a SINAD of 80dB and a dynamic range of 83dB, measured over a 10kHz signal bandwidth and using an analog supply voltage as low as 0.9V. The measured power dissipation is a mere 0.2mW at 0.9V supply.
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