Acacia Semiconductor to Present at ISSCC 2006
Update: Acacia Semiconductor has been bought by S3 Group on October 31st, 2007.
CAPARICA, Portugal -- January 30, 2006 — Acacia Semiconductor announced today that co-founder Dr. Goes et. al. will be presenting a paper at the IEEE International Solid-State Circuits Conference, to be held in February 5-9th, 2006, in San Francisco, USA.
The paper entitled “A 0.9V Sigma-Delta Modulator with 80dB SNDR and 83dB DR using a Single-Phase Technique” is part of the Oversampling ADCs Session 3.7.
The paper is the result of a joint R&D initiative with Universidade Nova de Lisboa and presents new design techniques that simplify the design, reduce die area and improve the energy-efficiency of sigma-delta ADCs, all fundamental requirements demanded by a growing number of portable systems spanning from voice to biomedical applications.
“The ISSCC is the most important forum for semiconductor design innovation in the world and we are delighted to see our design team recognized as a leader in analog design”, said Bernardo Henriques, CEO of Acacia Semiconductor.
The modulator is a second-order switched capacitor sigma-delta modulator featuring a 5.128MHz clock rate, an over-sampling rate of 256, a typical input differential voltage range of 1Vp-p and an input signal bandwidth of 10kHz. The circuit was fabricated in a 0.18µm CMOS process, occupies an ultra-small core die area of 0.06mm2, and was first-time-right.
Silicon characterization results show an SNR of 82dB, a SINAD of 80dB and a dynamic range of 83dB, measured over a 10kHz signal bandwidth and using an analog supply voltage as low as 0.9V. The measured power dissipation is a mere 0.2mW at 0.9V supply.
|
Related News
- Sankalp Semiconductor to present technical paper at CDNLive Bangalore
- Sankalp Semiconductor to Exhibit & Present at Design & Reuse IPSoC Santa Clara 2019
- ISSCC 2019: eSilicon to present a paper and demonstrate 7nm 56G DSP SerDes operation over a five-meter cable assembly
- Sankalp Semiconductor to present technical paper at CDNLive Bangalore
- Sankalp Semiconductor to Exhibit & Present at Design & Reuse IPSoC China 2018
Breaking News
Most Popular
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
- Silicon Creations Reaches Milestone of 10 Million Wafers in Production with TSMC
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Analog Bits to Demonstrate Numerous Test Chips Including Portfolio of Power Management and Embedded Clocking and High Accuracy Sensor IP in TSMC N3P Process at TSMC 2024 North America Technology Symposium
- Alphawave Semi: FY 2023 and 2024 YTD Trading Update and Notice of Results
E-mail This Article | Printer-Friendly Page |