Summit Design Unveils Panorama, The First Fully Integrated Design, Debug, and Implementation Solution for Embedded System on Chips

Enables Architectural Analysis Prior to Commitment with Specific Cores or IP and Eliminates the Need for Full-Functional Software Development

Los Altos, Calif. – March 27, 2006 – Summit Design, Inc., a leading provider of electronic system-level (ESL) and hardware description language (HDL) design solutions, today unveiled Panorama™, a complete hardware/software co-design and simulation solution that enables true architectural exploration and performance analysis. 

Panorama provides users with a rapid and efficient way to evaluate system-level architectural implementation options.  It enables concurrent development of the hardware and software portions of embedded System on Chips (SoCs), and it delivers the flexibility and accuracy needed to optimize architectural implementations early in the design effort.

The architectural decisions made for today’s multi-million gate embedded SoCs typically impact performance, cost, and power more than the implementation details, such as software compilation, logic synthesis, and place and route,” said Emil Girczyc, President and CEO of Summit Design, Inc.  “Panorama delivers the ability to fully evaluate and optimize the system-level architecture in the beginning of the design process, reducing the risk of an expensive over-designed or under-designed system.”

Panorama enables real-time application emulation of both the hardware and software portions of an embedded SoC - a truly critical capability in the design process that can help to reduce overdesign and its associated costs.  

Panorama allows system architects, software developers, and hardware designers to quickly and efficiently converge on the optimal architecture for their project needs.  The diverse users are able to compare various options before committing to a specific implementation.

Panorama is ideal for evaluating architectural implementation choices, such as single-versus multi-core software partitioning (as well as type of cores), third-party IP selection, real-time operating system (RTOS) selection, algorithm development, bus and memory selection, and the effect of hardware implementation on the application performance.

With Panorama, software developers can design, prioritize and partition the full embedded application software of the system onto a multi-core architecture without the need for integration with an instruction set simulator (ISS). 

“Understanding the effects on resources, such as operating system queues, buffers and system cache, makes software performance and partitioning a key element in embedded SoC design,” said Hagay Zamir, Director of System Architecture Products for Summit Design. “With its unique ability to provide generic operating system calls, Panorama allows designers to replace the operating system at any stage of the design, and test the impact on performance. Once the optimum solution is determined in Panorama, the developers can generate the code needed for the target platform. It is these capabilities that also allow design teams to test various processor cores, or multiples of the core, and the resulting impact on system-level performance.”

Panorama is available in three configurations:

• Panorama SPD™ (software platform development) provides software emulation for the target operating system and cores. While typical software architecture design requires only a simple model of the hardware, Panorama SPD provides full SystemC co-simulation capabilities for maximum flexibility.
• Panorama HPD™ (hardware platform development) includes the tools needed for SystemC hardware design. It includes Visual Elite™ for functional modeling design and verification, and also Vista™, the integrated development environment (IDE) that combines both hardware and software concepts to speed the design and debug of complex systems. In addition, Panorama HPD includes System Architect™, Summit Design’s established architectural exploration and analysis product, allowing fast and simple construction of the hardware platform. Full links to HDL design and co-simulation are supported.            
• The third option, Panorama VPD™ (virtual platform development), is the superset of both packages.  It includes the capabilities for hardware and software co-design, co-simulation and timing verification. Panorama VPD enables software execution on the evolving hardware platform for optimal architectural analysis.

Demonstrations of Panorama will be provided April 4th-6th, 2006, in Summit Design’s booth, #3329, at the Embedded Systems Conference Silicon Valley http://www.embedded.com/esc/sv/ 

Pricing and Availability
Panorama is available today.
The list price for Panorama SPD is US$35,000.
Panorama HPD is listed at US$55,000. 
Panorama VPD is list priced at US$75,000.

About Summit Design

Summit Design's industry-leading ESL and HDL solutions enable SOC companies to deliver products that meet system-level performance and power targets with dramatically reduced schedule risk. Summit's products address engineering challenges met during the specification and implementation design phases of complex hardware/software systems.

Panorama™ allows designers to perform real-time application emulation of both the hardware and software portions of an embedded SoC, before core and IP selections are finalized. System Architect™ enables massive increases in design complexity and performance by analyzing architectural tradeoffs to arrive at optimized system specifications. Vista™ and Visual Elite™ ensure swift, successful design modeling and implementation in SystemC, Verilog, and VHDL.

 Top electronics companies worldwide, including leaders in the wireless, automotive, and consumer electronics space, have achieved dramatic reductions in design cycle time through their use of Summit's products. Summit Design is headquartered in Los Altos, California, with offices throughout the US, Europe, Japan, Israel, and ROA.

To learn more, please visit http://www.sd.com