 |
Arithmatica Updates CellMath Tools for Power Optimization and Tighter Flow Integration for Verilog Users
Announces Sequence partnership to ensure consistent, significant power improvements PALO ALTO, Calif. - April 5, 2006 - Arithmatica, Inc., the first company focused solely on using advances in silicon math algorithms to lower costs and power and increase speed for math-intensive ICs, today announced version 3.0 of their CellMath datapath design tools. The milestone release incorporates power-knowledgeable synthesis and an extended Verilog interface capable of specifying robust datapath structures. Arithmatica has also entered into a partnership with Sequence Design to ensure that designers of complex SOCs can use both CellMath, for data path, and PowerTheater, for other blocks and full chip to achieve significant power improvements. Initial users of the new CellMath tools have reported typical ten to twenty percent power reductions in complex datapath circuits. The power optimization features are released for production use and the Verilog interface has been beta-released to current licensees and is expected to be production released this calendar quarter. New CellMath Designer 3.0 features include:
Teranetics results "The winners in the 10GBASE-T market will be defined by the highest performance and most power efficient designs. Arithmatica's CellMath Designer enabled our team to significantly reduce overall chip power and reduce datapath area while meeting the throughput requirements in our critical signal processing blocks," said Sridhar Begur, Teranetics' Director of ASIC Design. "In addition, the behavioral models provide an elegant way to formally verify the netlist easing the verification bottleneck typical in complex signal processing designs." Vic Kulkarni, CEO of Sequence Design stated, "We welcome Arithmatica as our newest In-Sequence partner. Our collaboration in low power datapath design will help our common customers, as illustrated by Teranetics' achievement, to differentiate with power-aware designs. Our continuing joint technology in the RTL modeling area will bring improved predictability at the datapath behavioral modeling stage." Sunil Talwar, Arithmatica's CTO commented, "Both the performance and portable segments are limited by power dissipation. Verilog-driven, power-knowledgeable datapath synthesis provides users another unique degree of freedom - architecture selection - to use in addition to current power management techniques. By incorporating CellMath tools into their flows, datapath designers will gain an incremental 10-20 percent power improvement in addition to their current results." Pricing and Availability About Arithmatica
|
| |||||||||||||||||
