Evatronix Verifies a Core with 50 Billion Legal Configurations Using Aldec Tools

Update: Cadence Completes Acquisition of Evatronix IP Business (Jun 13, 2013)

Gliwice, Katowice, Poland; Henderson NV, USA - April 13, 2006 --Evatronix, a silicon Intellectual Property (IP) provider completed earlier this year the development of the R8051XC – a new version of a microcontroller core based on an evergreen 8051 instruction set. The core was first announced by Evatronix partner - CAST, Inc., at DesignCon’2006. It leverages six years and 100+ chip designs worth of experience Evatronix earned with its R80515 and R8051 best selling IP cores. The R8051XC core is extremely configurable: it allows in theory up to 50 billion legal configurations. Verifying the core with that many configurations has taken Evatronix's quality assurance effort to a whole new level.

Evatronix relied on Aldec's HDL simulation technology to develop and verify this core as it did in the past for other products from the broad portfolio. For an IP Core provider an HDL simulator is a key software component. It is absolutely indispensable says Wojciech Sakowski, Evatronix co-founder and CSO. Aldec's simulator is a tremendous value for money. For the price, nothing near that good is available on the market. Aldec’s Active-HDL environment satisfies all our requirements for source code creation and debugging. It has a source code debugger, a waveform viewer, data flow diagrams generated on the fly. A memory viewer is also available, an important touch for a company like ours that develops processor cores. While we use simulators from other parties for the sake of script compliance testing, we have relied on Aldec's simulator as the key tool in our development process for several years. We still have some legacy Active-HDL 3.6 seats that we acquired back in 1999. They are used by interns that we accommodate in the company every year and for running regression tests on our older cores.

Despite a huge number of allowable configurations, the orthogonality of many options allowed to achieve full code coverage while simulating only a little more than 100 different configurations. These simulations took a lot of time in the verification phase, especially given that the test set for this core is very extensive (verification documentation itself consists of 800 pages). Nevertheless, to ensure the highest degree of reliability each custom configuration that does not match exactly one of these 100+ variants verified thoroughly during the R8051XC development runs a full set of regression tests before being delivered to the customer. The faster Evatronix can complete such final validation process, the sooner it can deliver a customized core to the customer.

Our customer base is growing quickly. Therefore we have just signed another deal with Aldec to add more simulation seats and maximize simulation throughput Sakowski explains. Possibility to use Active-HDL simulator in a batch mode while using Active-HDL GUI for design entry pushes ROI for these tools to yet a higher level. We have developed in-house job management system that monitors simulator license usage in our VPN and claims each unused license to run queued regression test jobs.

Evatronix has started to adopt the assertion-based verification methodology recently, based on Property Specification Language (PSL) as well as Transaction Level Modeling in SystemC as means to provide an abstract view of its peripheral controllers, suitable for early software development.

Aldec’s strive for support of new verification technologies before they become mainstream design practices enables us to keep up in step with our customers’ expectations related to methodologies we use in the design process says Miroslaw Bandzerewicz, Evatronix quality assurance manager. Therefore we are looking to extend our installed simulator base with Aldec Riviera licenses as it supports PSL as well as SystemC.

When Evatronix embraces Riviera it will also be able to replace its home-grown simulation job management scripts with a professional server farm software delivered by Aldec as a turnkey solution. Aldec will be also providing technical support for all new tools and methodologies that Evatronix is now adopting. The companies are located within a 30 minutes drive, so an on-site support is easy and gives us valuable firsthand feedback. We are also looking forward to ideas on possible improvements to our technology and usability of our tool says Michal Pacula, technical support manager at Aldec-ADT, Poland.  

About R8051XC:

R8051XC is an evolutionary step for the Evatronix 8051 microcontroller core product line. It was developed to accommodate experiences gained with 100+ chips in which older members of Evatronix 8051 product line were implemented. The new version of the core achieves an average eight times performance increase over the original 80C51 and may be easily configured to match customer needs. Features such as the exact configuration of a peripheral set, number of interrupt lines and priority levels, number of DPTR registers and size of program memory, even presence of some rarely used but costly (in terms of hardware) instructions depend on customer decision. SPI and I2C controllers are available as low cost add-on options. On chip debug support is an option, too. User may choose between Evatronix proprietary solution interfaced to Keil software development environment and OCI circuitry from First Silicon Systems (FS2). Customer documentation includes over 200 pages of the Design Specification, 100 pages of the Verification Specification and 800 pages of the Test Plan that outlines over 1500 test cases used to verify the core.

R8051XC IP core is available world wide from CAST, Inc. (www.cast-inc.com) or its sales partners and in the continental EU countries also directly from Evatronix.

About Active-HDL and Riviera

Active-HDL is a Windows-based, integrated, HDL-based design entry and simulation environment. It provides engineers and design teams with tools for efficient and vendor independent design implementation and testing.

Riviera is a high-performance ASIC and large FPGA verification solution. Its common kernel simulator supports VHDL, Verilog, EDIF, SystemC, SystemVerilog, SVA, OVA and PSL in a unified, advanced debugging environment. Riviera can be used either on the engineer desktop, or for massive batch processing controlled through a web-based interface.

About Evatronix:

Evatronix SA, headquartered in Bielsko-Biala, Poland was established in 1991 as a value added reseller of EDA & CAD systems. Since 1997 Evatronix has been developing electronic virtual components (IP cores) and since 2003 it has been providing electronic design services. Evatronix main design office is located in Gliwice, which guarantees easy access to the talent pool of graduates from Silesian University of Technology. More information on Evatronix can be found on the company web site at http://www.evatronix.pl.

About Aldec:

Aldec, Inc., a 20-year EDA tool provider, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux and Windows platforms. Continuous innovation, superior product quality and a total commitment to customer service comprise the foundation of Aldec's strategic objectives. Additional information about Aldec is available at http://www.aldec.com.