TSMC Unveils First 65-Nanometer Data-Driven DFM Design Ecosystem

SAN JOSE, Calif.--May 15, 2006--Taiwan Semiconductor Manufacturing Company today unveils an extensive 65nm DFM Compliance Design Support Ecosystem that's driven by a manufacturing-based unified data format to channel design-for-manufacturing (DFM) capabilities through selected electronic design automation (EDA) tools directly to designers' workstations.

TSMC developed the unified format to align DFM tools -- Lithography Process Check (LPC), Chemical Mechanical Polishing (CMP) Analysis and Critical Area Analysis (CAA) -- to TSMC's manufacturing data format. This allows designers to use the same DFM data file irrespective of the tool or vendor. It also enables simplified use, management and updates to DFM analyses using these tools.

Designers can download an encrypted TSMC DFM Data Kit (DDK), compiled in the DUF format, and run TSMC-qualified DFM tools directly on their workstations, with results that are consistent with the company's own internal DFM results.

The Ecosystem results from a year-long collaboration between TSMC and its design partners to shorten the 65nm design cycle and accelerate time-to-volume and time-to-market for leading-edge products.

"This is a comprehensive collaboration to deliver 65nm DFM-compliant products and design services to the designer's desk top," said Edward Wan, Senior Director of Design services marketing for TSMC. "Basically, we've defined what it means to be DFM compliant, and we've helped our Ecosystem partners to achieve that compliance."

The TSMC 65nm Design Support Ecosystem defines a DFM-compliant IC design infrastructure. By aggressively driving its process knowledge up the design chain, TSMC and its Design Service Alliance partners improve 65nm design quality.

DFM Tools Qualification -- TSMC worked with a select number of third-party EDA vendors to qualify their tools. The qualification ensures that the results from the tools are consistent with those from TSMC's own internal results. Run-time performance and user-friendliness are also essential parts of this qualification procedure. This qualification procedure involves tools from Anchor Semiconductor, Cadence Design Systems, Clear Shape Technologies, Magma Design Automation, Mentor Graphics, Ponte Solutions, Predictions Software, and Synopsys, Inc.

IP and Library Compliance -- TSMC has defined the industry's first set of IP and Library compliance criteria which includes running checks, such as DFM Layout Parasitic Extraction (LPE), a layout enhancer, and Lithography Process Check (LPC), using TSMC's DFM database to achieve optimal DFM results in terms of timing accuracy and hot-spot removal. Through an intensive training program, the company assists third-party IP and library vendors to achieve this DFM compliance.

Design Center Alliance (DCA) Collaboration -- TSMC has worked with an initial set of DCA members to hone their ability to implement 65nm DFM-compliant design practices. Some DCA partners have already helped 65nm early adopters to achieve successful tape outs.

TSMC DFM-Compliance Initiative

Today, the DFM-compliance initiative encompasses 18 companies from the IP, library, EDA and design center communities, including: Alchip, Anchor, Aprio, AnalogBits, ARM, Blaze DFM, Cadence, Clear Shape, Dolphin Technology, Fastrack, Global Unichip, Magma, Mentor, Ponte, Predictions, Qthink, Synopsys and Virage Logic.

About TSMC's 65nm Process Technology

In October 2005, TSMC announced it had successfully completed its first 65nm prototype runs for five major customers' designs and multiple 3rd party IP designs. Just last month, TSMC helped announce a customer's 65nm volume production. Along the way, many TSMC library, IP, and EDA tool developers have validated their products on the technology, ensuring that their capabilities are process-proven.

TSMC's 65nm success builds on the company's industry leading 0.13-micron and 90nm track records. TSMC estimates that the 65nm production will ramp during 2006, and the company will also launch 65nm prototyping shuttles every other month.

TSMC's 65nm Nexsys(SM) technology is the company's third-generation semiconductor process employing both copper interconnects and low-k dielectrics. It is a 9-layer metal process with core voltages of 1.0 or 1.2 volts, and I/O voltages of 1.8, 2.5 or 3.3 volts. The new technology offering supports a standard cell gate density twice that of TSMC's 90nm Nexsys(SM) process. It also features very competitive 6T SRAM and 1T embedded DRAM memory cell sizes. In addition, this technology offering includes mixed signal and radio frequency functionality to support analog and wireless design, embedded high density memory to support integration of logic and memory, and electrical fuse to support customer encryption needs.

About TSMC

TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry industry's largest portfolio of process-proven library, IP, design tools and reference flows. The company operates two advanced twelve-inch wafer fabs, five eight-inch fabs and one six-inch wafer fab. TSMC also has substantial capacity commitments at its wholly owned subsidiaries, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC is the first foundry to provide 65nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please see http://www.tsmc.com.