400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
OCP-IP Releases Functional Coverage Guidelines; Guidelines eliminate the need for ''best guess'' verification by engineers
In a pseudo-random based verification environment in which the stimuli are randomly generated within a set of constraints, a solid Functional Coverage indicates which parts of the state space were covered, and which parts were not. For the uncovered corners, the generation constraints must be tightened, or specific directed tests must be written.
Work on the Functional Coverage was completed by the OCP-IP Functional Verification working group including representatives from: Jeda Technologies, MIPS, Sonics Inc, Synopsys, Texas Instruments, TransEDA, and Yogitech. This work compliments a set of formal compliance checks already released by the FVWG in October 2005.
"The new coverage guidelines make it easier for engineers to have even greater verification coverage as a part of the OCP socket," said Jeroen Vliegen, System Engineer for Texas Instruments and member of the OCP-IP Functional Verification Working Group. "It was a pleasure leading the collaboration between such productive members of OCP-IP's FVWG."
"The configurability of the OCP protocol fits naturally with today's Functional Coverage driven verification methodology," said Steve McMaster, Senior Staff Engineer for Synopsys and Chairman of the OCP-IP FVWG. "It was a pleasure to participate in this important work with such a dynamic group."
“Presenting defined functional coverage guidelines to the industry further strengthens the value and utility of the OCP standard”, said Silvano Motto, CEO of Yogitech. “This significant accomplishment was made possible by the expert contributions of the OCP-IP FVWG team, in which I am very proud Yogitech participated as a verification IP provider.”
“ The guidelines produced by our Functional Verification Working Group are yet another extremely valuable addition to OCP-IP’s robust, thriving infrastructure, said Ian Mackintosh, president OCP-IP.” “We are proud of the leading-edge work completed by our Functional Verification Working Group.”
Members may download and review a copy of the compliance checks by visiting the member’s only section at www.ocpip.org
About OCP-IP
The OCP International Partnership Association, Inc. (OCP-IP), formed in 2001, promotes and supports the Open Core Protocol (OCP) as the complete socket standard ensuring rapid creation and integration of interoperable virtual components. OCP-IP's Governing Steering Committee participants include: Nokia [NYSE: NOK], Texas Instruments [NYSE: TXN], Toshiba Semiconductor Group (including Toshiba America TAEC), and Sonics. OCP-IP is a non-profit corporation delivering the first fully supported, openly licensed, core-centric protocol comprehensively fulfilling system-level integration requirements. The OCP facilitates IP core reusability and reduces design time, risk, and manufacturing costs for SoC designs. VSIA endorses the OCP socket, and OCP-IP is affiliated with VSIA. For additional background and membership information, visit www.OCPIP.org.
|
Related News
- OCP-IP Announces Support for Cadence's Assertion Based OCP Protocol Verification IP
- OCP-IP Standardizes on Synopsys' DesignWare Verification IP for OCP-IP's CoreCreator Verification Toolset
- Imperas releases new updates, test suites, and functional coverage library to support the rapid growth in RISC-V Verification
- OCP-IP Releases OCP Debug Socket Specification 2.0
- OCP-IP Releases OCP 3.1 Specification into Member Review
Breaking News
- PUFsecurity Unveils Next-Gen Crypto Coprocessor PUFcc7 Featuring High-speed Performance and TLS 1.3 Support
- SEMIFIVE Starts Mass Production of its 14nm AI Inference SoC Platform based Product
- VeriSilicon's complete Bluetooth Low Energy IP solution is fully compliant with LE Audio specification
- TASKING and Andes Announce FuSa Compliant Compiler Support for Andes RISC-V ASIL Compliant Automotive IP
- Efabless Launches an "AI Wake Up Call" Open-Source Silicon Design Challenge
Most Popular
- Qualitas Semiconductor and Ambarella Sign Licensing Agreement
- ZeroPoint Technologies Signs Global Customer to Bring Hardware-Accelerated Compression to Hyperscale Data Centers
- Chiplet Interconnect Pioneer Eliyan Closes $60 Million Series B Funding Round, Co-led by Samsung Catalyst Fund and Tiger Global Management to Address Most Pressing Challenge in Development of Generative AI Chips
- Intel and Arm Team Up to Power Startups
- Alphawave Semi and InnoLight Collaborate to Demonstrate Low Latency Linear Pluggable Optics with PCIe 6.0® Subsystem Solution for High-Performance AI Infrastructure at OFC 2024
E-mail This Article | Printer-Friendly Page |