Matrix preps 64-Mbyte write-once memory
Matrix preps 64-Mbyte write-once memory
By Margaret Quan, EE Times
December 19, 2001 (3:24 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011219S0041
MANHASSET, N.Y. Matrix Semiconductor Inc. has come out of stealth mode to disclose a stacked, eight-layer memory that can be made in standard CMOS fabs. The company predicts the devices will lead to a new, low-cost category of memory chips for consumer products. Using a 3-D fabrication method that deposits layers of circuits with a modified CMOS process, the technique can yield nine to 10 times the amount of chips per a given wafer, providing a cost advantage over traditional flash memory, according to Matrix (Santa Clara, Calif.). Plans call for introduction of the company's first device, a 64-Mbyte write-once memory chip called the Matrix 3-D Memory, in the first half. The "consumable memory" chip is expected to compete with such low-cost consumable storage media as camera film and audio cassette tapes. The first chips will be manufactured by foundry partner Taiwan Semiconductor Manufacturing Co. using a 0.25-micron process. Matr ix executives said the first-generation product has been taped out. If the technology works as promised, it would enable immediate increases in density without requiring advances in lithography. "If they can really do this and produce working devices, it is very hot," said Richard Wawrzyniak, an analyst at Semico Research (Phoenix). "People have been trying to do this [in the lab, with exotic materials] for 30 years, and no one has been able to do it." The company envisions its chips being cheap enough to be sold in multipacks at grocery checkout counters and used to store music in portable MP3 players, images in digital cameras or content in programmable handheld personal digital assistants and set-top boxes. Matrix is working with partners to bring memory products to market, the executives said, promising announcements soon. Although the company did not identify its partners, they may include some of the investors that contributed $80 million in funding to the venture, including Microsoft Corp ., Thomson Multimedia, Eastman Kodak and Sony Corp. The partners would commercialize the devices to be compatible with standard flash formats and interchangeable with flash cards. Three product categories are planned: blank memory cards; cards sold preloaded with content, such as software or music; and standard memory packages, for use in embedded applications such as PDAs and set-top boxes. Matrix executives declined to reveal much about the technology, but chief executive Dennis Segers said it borrows from both the LCD process, wherein thin-film transistor layers are deposited on glass, and multilayer metal processes used to build ASICs. But while ASIC processes use multilayer interconnect for wiring, Matrix Semiconductor is "building circuits on those extra layers, with active circuits and interconnects in the same layers, " said Segers. The company said it sees no limit to the number of layers that could be added to a device.
Related News
- Denali Databahn Memory Controller Core Once Again Selected By Silverback Systems For Storage Network Access Processor Family
- Rambus Advances AI 2.0 with GDDR7 Memory Controller IP
- RAAAM Memory Technologies Closes $4M Seed Round to Commercialize Super Cost Effective On-Chip Memory Solutions
- sureCore announces low power memory compiler for 16nm FinFET
- Spectral Releases Advanced Quality Assurance & Data Analytics tool to validate advanced node Memory Compilers
Breaking News
- Keysight, Synopsys, and Ansys Deliver Radio Frequency Design Migration Flow to TSMC's N6RF+ Process Node
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Leveraging Cryogenics and Photonics for Quantum Computing
- Kalray Joins Arm Total Design, Extending Collaboration with Arm on Accelerated AI Processing
- Credo at TSMC 2024 North America Technology Symposium
Most Popular
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
- Silicon Creations Reaches Milestone of 10 Million Wafers in Production with TSMC
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Analog Bits to Demonstrate Numerous Test Chips Including Portfolio of Power Management and Embedded Clocking and High Accuracy Sensor IP in TSMC N3P Process at TSMC 2024 North America Technology Symposium
- Alphawave Semi: FY 2023 and 2024 YTD Trading Update and Notice of Results
E-mail This Article | Printer-Friendly Page |