Faraday Pioneers in Providing On-Chip Variation (OCV) Information for Cell Libraries
Faraday's advanced built-in OCV library provides location, level, and cell-based OCV analysis to address the effects of on-chip statistical process variation, which can no longer be ignored in 0.13 µm designs or below. Most significantly, it improves timing accuracy and reduces the effort for timing closure, thus increasing the productivity for 0.13 µm timing signoff. The OCV methodology can save the chip size while speeding up time to market and assuring of high product yield, and it is so very easy to implement!
"With our new advanced OCV library and methodology, Faraday has established itself as the innovator and leader in 0.13 µm static timing analysis and signoff," said Dr. George Hwang, Vice President of R&D and International Business, Faraday. "Its introduction makes us the first ASIC/SIP vendor who offers the back-end intra-die timing analysis total solution for 0.13 µm ASIC designs."
About Faraday's LLC-OCV Library and Methodology
The traditional OCV methodology uses a constant derating factor and may impose unnecessary performance penalties on 0.13 µm designs, including reduced performance, larger die sizes and longer design cycles. Faraday's advanced OCV library and methodology use variable derating factors based on the gate level, physical location, and the respective used cell to select the optimal derating factor for each timing path. This enhances the accuracy of timing analysis, eliminates unnecessary timing violations, and allows design teams to rapidly achieve timing closure.
The 0.13 µm HS library with the OCV technology is currently available. The 90 nm series will be ready by Q1 2007.
|
Faraday Technology Corp. Hot IP
Related News
- Faraday Delivers a Complete Set of Cell Libraries and Memory Compilers for UMC 28nm HPC Process
- Faraday Delivers a Complete Set of UMC 28nm Cell Libraries and Memory Compilers
- Analog Bits Unveils Integrated Sensor Macro Family
- Synopsys PrimeTime Advanced On-chip Variation Analysis Enables Renesas to Accelerate Timing Closure at 65-nm and Below
- Cadence Introduces EMX Designer, Delivering More Than 10X Increased Performance for On-Chip Passive Component Synthesis
Breaking News
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
- Controversial former Arm China CEO founds RISC-V chip startup
- Fundamental Inventions Enable the Best PPA and Most Portable eFPGA/DSP/SDR/AI IP for Adaptable SoCs
- Cadence and TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design
- Numem at the Design & Reuse IP SoC Silicon Valley 2024
Most Popular
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Qualitas Semiconductor Appoints HSRP as its Distributor for the China Markets
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
E-mail This Article | Printer-Friendly Page |