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Chipworks 65-nm Virtex-5 Study Validates Customer Benefits of Xilinx Dual-Foundry Strategy
In-depth structural analysis and DC transistor characterization proves that devices manufactured by Toshiba and UMC equally meet high-performance specifications SAN JOSE, Calif., December 21, 2006 – Xilinx, Inc. the world’s leading FPGA company, today announced that Chipworks (ON, Canada), the industry leader in reverse engineering and analysis of semiconductor chips and systems, has completed an in-depth technical study of twin samples of the Xilinx 65-nm XC5VLX50 Virtex™-5 FPGA, manufactured by foundry partners Toshiba and UMC. Based upon structural analyses and DC transistor characterization (to compare the impact of structure on performance), Chipworks has concluded that 65-nm devices manufactured by either foundry meet high-performance Virtex-5 specifications. “Our observations indicate that Xilinx has successfully developed Virtex-5 with two different foundries – each with differences in their 65-nm process – while attaining Xilinx performance specifications,” says Terry Ludlow, CEO and Founder, Chipworks. “The relationships with Toshiba and UMC ensure that Xilinx remains at the forefront of technology, allowing them to expedite 65-nm device manufacturing, while hedging against process problems and increasing manufacturing capacity. It appears that a multi-foundry strategy – industry standard for leading semiconductor companies like Texas Instruments – has also proven successful for Xilinx, a leading fabless semiconductor company.” The Chipworks 65-nm Virtex-5 study is available for purchase now at http://www.chipworks.com. Virtex-5 is among five leading-edge 65-nm devices analyzed by Chipworks in recent months, including Intel’s Presler and Yonah chips, and a Matsushita SoC part targeted at the consumer market. Chipworks is currently looking at another UMC-fabbed 65-nm part, using Texas Instruments’ technology. Virtex-5 devices manufactured by UMC and Toshiba have 12 metal layers (11 copper and one aluminum) and are fabricated from 300 mm wafers. Characteristic of advanced 65nm processes, both use nickel silicide self-aligned technology, low-k dielectrics (although different materials), and wafer rotation plus nitride strain to enhance transistor performance. In addition, Xilinx has continued its use of triple oxide technology. “This advanced processing results in a 30% increase in speed and a 35% reduction in power compared with the earlier Virtex-4 technology,” explained Michael Hart, senior director of semiconductor technology development at Xilinx. The Chipworks report provides a detailed look into the structural and process elements Xilinx used to achieve these performance improvements in the Virtex-5, while dropping the cost by 45 percent from earlier generations. According to Chipworks, technical analyses are beneficial to their customers, allowing engineers to learn the ins and outs of the world’s most advanced chip-making processes from semiconductor leaders and to use this information to improve their own designs and speed time to market. To order copies of the Chipworks 65-nm Virtex-5 report, go to:
To purchase the Virtex-5 DC transistor characterization reports on these devices, please contact insidetechnology@chipworks.com. About Chipworks About Xilinx
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