Texas Instruments fields high-speed 'C64x DSP

Texas Instruments fields high-speed 'C64x DSP
By Darrell Dunn, EBN
June 14, 2000 (1:55 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000614S0019

Texas Instruments Inc. has furnished new details as to the memory and peripheral systems that will be used as part of its upcoming 'C64x family, a high-performance DSP expected to operate initially at around 700-MHz.

TI's TMS320C64x DSP, first announced in February and expected to begin sampling by the end of the year, will have a two-level cache memory, a 32-channel enhanced direct memory access (EDMA) controller, and multiple external buses to support high-speed connections to external memories, peripherals, and host processors.

The first device in the family, the TMS320C6401, is expected to debut with performance around 700 MHz, with production scheduled for midyear 2001. TI plans to scale the family to 1.1-GHz performance.

"The 'C64x memory and peripheral system provides peak system performance for the world's fastest DSPs," said Henry Wiechman, TMS320C6000 marketing manager for TI, speaking from the Embedded Processor Forum in San Jose.

"Developers who move to this generation will be ahead of the curve as TI introduces code-compatible DSPs that scale to achieve more than twice today's performance with a variety of different memory and peripheral configurations to meet the needs of a broad range of applications," he said.

The two-level cache will have 16 Kbytes of memory in each, four times the cache memory available in TI's existing TMS320C6211 DSP.

The EDMA controller will be capable of transferring more than 2.6 Gbytes/s of sustained bandwidth. With a total of 85 linkable parameter sets, and four independent priority transfer cues, the EDMA maximizes concurrency and can scale to support multiple peripherals, Wiechman said.

A 64-bit synchronous external memory interface (EMIF) combines with a 16-bit secondary EMIF for external peripherals and a 32-bit host port interface (HPI) to provide more than 1.8 Gbytes of bandwidth on initial implementations of the family.

Other I/O peripherals include three multi-channel buffere d serial ports (McBSPs) that can compress and expand up to 128 T1/E1 channels each, as well as additional networking and video interfaces.