English
Rockwell seeks 50 percent design cycle reduction
Richard Goering, EE Times
(03/15/2007 12:10 AM EDT)
SAN JOSE, Calif. — Avionics electronics firm Rockwell Collins has initiated a five-year effort to cut its engineering cycle time by 50 percent, according to Linda Snow-Solum, senior director of enterprise infrastructure management at that company. In a presentation Wednesday (March 14), she outlined Rockwell's drive to integrate tools and processes at the enterprise level.
Snow-Solum was a speaker in the management track at the Mentor Graphics User-to-User conference. She discussed how Rockwell Collins is centralizing its tool selection and support, reducing engineering handoffs, cutting schematic development time, and using an internally developed "peer review" tool.
(03/15/2007 12:10 AM EDT)
SAN JOSE, Calif. — Avionics electronics firm Rockwell Collins has initiated a five-year effort to cut its engineering cycle time by 50 percent, according to Linda Snow-Solum, senior director of enterprise infrastructure management at that company. In a presentation Wednesday (March 14), she outlined Rockwell's drive to integrate tools and processes at the enterprise level.
Snow-Solum was a speaker in the management track at the Mentor Graphics User-to-User conference. She discussed how Rockwell Collins is centralizing its tool selection and support, reducing engineering handoffs, cutting schematic development time, and using an internally developed "peer review" tool.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related News
- Synopsys Collaborates with GLOBALFOUNDRIES to Deliver Up to 50 Percent Power Reduction for Designs Using the 22FDX Platform
- Xilinx Planahead v2.2 Tool Delivers Up To 2X Performance Boost And 50% Design Cycle Reduction For Virtex-4 FPGAs
- DecaWave Deploys Synopsys TetraMAX II ATPG on Latest Automotive Design to Lower Test Time 50 Percent and Speed Runtime by 10x
- Accusonus Achieves 60 Percent Reduction in Computational Cost of Speech Enhancement Software for Cadence Tensilica HiFi DSPs
- Fuji Xerox Reduces Silicon Area by More than 50 Percent Using Synopsys ASIP Designer
Breaking News
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Leveraging Cryogenics and Photonics for Quantum Computing
- Kalray Joins Arm Total Design, Extending Collaboration with Arm on Accelerated AI Processing
- Credo at TSMC 2024 North America Technology Symposium
- Cadence Reports First Quarter 2024 Financial Results
Most Popular
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
- Silicon Creations Reaches Milestone of 10 Million Wafers in Production with TSMC
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Analog Bits to Demonstrate Numerous Test Chips Including Portfolio of Power Management and Embedded Clocking and High Accuracy Sensor IP in TSMC N3P Process at TSMC 2024 North America Technology Symposium
- Alphawave Semi: FY 2023 and 2024 YTD Trading Update and Notice of Results