NEC Electronics tips high-level design initiative

NEC Electronics tips high-level design initiative
By Richard Goering,
May 16, 2000 (3:16 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000516S0022

SANTA CLARA, Calif. — In an attempt to bring system-level design to its ASIC customers, NEC Electronics Inc. this week is outlining phase one of its ACE-2 methodology initiative. NEC is identifying specific EDA tools and an overall methodology in a bid to shorten design times.

ACE-2 is a three-year, $30 million effort that looks to offer customers a three-month turnaround, from system spec to tapeout, for a 30-million gate design. The initiative hopes to accomplish that goal by 2002.

NEC Electronics isn't a provider of EDA tools, but its endorsement of third-party tools carries clout. Moreover, NEC is showing customers how the tools can fit into an overall flow, and it is providing scripts and interface software to ease that flow.

"NEC is an integrator of tools and methodologies," said Ka zu Yamada, general manager of NEC's Technology Foundation Division. "We combine the best tools in each area, give the path to customers and tell them to use this to get a good result."

While NEC's endorsement of a tool is a "strong suggestion," there's no requirement that ASIC customers use the ACE-2 tools, Yamada said.

One reason for the initiative is that conventional design methodologies don't work very well for multimillion-gate chips, he said. If customers can't design such chips, NEC can't build them. One expected outcome of ACE-2's second phase, slated for completion in March 2001, is to allow RTL signoff, which NEC does not currently support.

NEC benchmarks suggest that phase one can cut a 450-man-month effort to build a 2 million-gate chip to 300 man-months, Yamada said. Phase two could drop that figure to 200 months.

One design area addressed by phase one is intellectual property (IP) modeling. NEC has set forth a flow for internal designers and customers who are creating IP or who are modeling external IP for use in a system-on-chip design.

Tools endorsed

Individual tasks include hardware/software co-design and co-verification, software/firmware verification, and timing verification. EDA tools endorsed for IP modeling include Co-Ware's N2C, Cadence Design's Cierto VCC, CardTools' NitroVP, Synopsys' Eagle, Mentor Graphics' Seamless and Synopsys' Primetime.

Software verification comes next in phase one. Here, the intent is to use CardTools' NitroVP co-verification tool C/C++ hardware models for software/firmware verification.

Fast RTL verification is a third area. NEC's methodology claims to speed RTL verification two-fold with C/C++ models and Verisity's Specman testbench generation system.

In a fourth area — "interface to silicon design" — NEC cuts turnaround time by bringing in RTL design planning. The tool endorsed for that task is TeraForm, from Tera Systems.

The fifth design area, system evaluation, uses NEC's proprietary Corebest prot otyping board, along with Synplicity's Certify software, which maps net-lists into Corebest's FPGAs.

The ACE-2 initiative will stay at or above the RTL. Phase two will examine system analysis and hardware design and will bring in such tools as behavioral synthesizers. ACE-2 complements NEC's OpenCAD environment, which starts with RTL design and goes through silicon implementation.