Synopsys' Physical Synthesis Solution Adopted for Next Generation ARM Processor Cores

 

Synopsys' Physical Synthesis Solution Adopted for Next Generation ARM Processor Cores

Physical Compiler shortens timing closure cycle from over a month to less than two days

MOUNTAIN VIEW, Calif., May 15, 2000 -- Synopsys, Inc. [(Nasdaq: SNPS)] today announced that ARM [(LSE: ARM); (Nasdaq: ARMHY)] has adopted Synopsys' Physical Compiler as the timing closure tool for its intellectual property (IP) products. The adoption was based on the significant productivity (one month), performance (five percent) and area (seven percent) improvements, that were achieved by ARM on its complex integrated circuit design using Synopsys' Physical Compiler. In a single day, using Synopsys' Physical Compiler tool, ARM achieved a 15x overall productivity improvement in design time.

ARM, the industry's leading provider of 16/32-bit embedded RISC microprocessor solutions, previously used a traditional timing closure flow that included in-place optimization and traditional place and route tools. Prior to selecting Synopsys' Physical Compiler, ARM also evaluated other solutions that failed to overcome the timing closure problems experienced with the traditional flow.

"ARM is committed to achieving the highest performance possible for our designs," said Tudor Brown, chief technology officer for ARM. "Of all the solutions we tried, the results from Physical Compiler were the most impressive. Synopsys' Physical Compiler provided better performance and area numbers over the alternatives and significantly cut our design time. Our partners will benefit from the enhanced performance and productivity that Physical Compiler provides."

"The performance and productivity gain that ARM has achieved using Physical Compiler is consistent with the benefits other customers are experiencing," said Sanjiv Kaul, vice president and general manager, Synopsys' Physical Synthesis business unit. "The fact that Physical Compiler could easily be built on top of ARM's existing Synopsys Design Compiler synthesis investment, made it even easier for them to adopt our flow. We feel confident that Physical Compiler will continue to provide the type of results ARM needs, to rapidly deliver the highest performance processor cores to the time-sensitive portable communications market."

Synopsys' Physical Synthesis Solution

Pioneered by Synopsys, Physical Synthesis helps designers address the implementation challenges of next-generation ASIC and system-on-chip designs. Physical Synthesis brings key physical design considerations to the front-end, allowing RTL designers to achieve the highest quality area, timing and power quickly. The overall design flow includes Chip Architect design planner, Physical Compiler unified synthesis and placement tool and FlexRoute top-level router. It leverages industry-standard tools like Design Compiler(TM), Module Compiler(TM) and PrimeTime(R). Its proven interfaces to third-party solutions allow it to easily plug into an existing design flow.

About Synopsys

Synopsys, Inc. [(Nasdaq: SNPS)], headquartered in Mountain View, California, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems, and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com.
 

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