HD Lab, Inc. Releases "SystemC Behavioral Synthesis Style Guide"

SystemC-Based Design Coding and Methodology Guide Now Widely Available in Japan

Shin-Yokohama, Japan – July 23, 2007 -- HD Lab, Inc., announced today the availability of its "SystemC Behavioral Synthesis Style Guide”, a reference book that documents production-proven expertise and design techniques based on SystemC, the de facto standard for ESL design and verification.  

HD Lab has been actively engaged in SystemC design, verification and design methodology consulting for the past three years.  Based on its experience with real world client projects, HD Lab has accumulated and cultivated various design techniques and best practices using SystemC.  The design style guide documents these design techniques and expertise in a well organized, easily implementable manner.  The guide has been used by consultants at HD Lab, and proven at number of client design project sites in leading systems and semiconductor companies throughout Japan.  As compared to traditional RTL-based design methods, the SystemC design methodology described can yield significant savings in overall design cycle time anywhere from 1/3 to 1/2.  The guide includes examples of design blocks in excess of 3 million gates being designed using SystemC descriptions.  The guide also follows and implements JEITA SystemC working group’s proposal on behavioral synthesis guidelines.  

To achieve wider acceptance of behavioral synthesis, the style guide is written with a variety of design engineers in mind.  The style guide methodically defines and explains SystemC descriptions that will produce high quality circuits.  To assist in the adoption of behavioral synthesis, the style guide includes a rich set of coding examples as well as building methodologies for a verification environment.  The coding examples and templates described in the style guide will also be available for download, to further accelerate the first-time adoption of SystemC design techniques.

The highlights of the style guide are as follows:

1. Introduces a SystemC based design and verification methodology, and explains the benefits of using SystemC.

2. Explains the uniform coding rules for design reuse within the company and between different companies.  

3. Follows the organization and conventions of the popular “RTL Design Style Guide”.  (RTL Design Style Guide is the de facto RTL coding guideline published by STARC & HD Lab)

4. Presents circuit architecture, verification strategy and design methodology in a thorough and easy to follow style for both designers and design managers.

5. Presents key coding techniques in a systematic fashion to allow an expedited learning curve.  The initial learning curve savings can be as great as 50%.

6. Provides detailed behavioral synthesis examples following descriptions defined by Forte Design Systems Cynthesizer™, the most popular and widely accepted SystemC synthesis tool, which is in production use in more than 25 of the top systems and semiconductor companies. Cynthesizer automatically generates high-quality hardware designs from SystemC.

7. Provides behavioral synthesis design examples, coding templates and sample codes for download from HD Lab, Inc’s web page (for no incremental cost).

Future Updates to Include English Version

Regular updates to the style guide are planned as new versions of tools in synthesis and verification becomes available.  HD Lab is also actively participating in the JEITA (Japan Electronics and Information Technology Industries Association) SystemC task group.  HD Lab will be actively seeking to encourage world-wide acceptance of the “SystemC Behavioral Synthesis Design Style Guide” through its planned release of an English version in 2008.  

“With the availability of the design style guide, new ESL design style will be widely accepted,” said HD Lab, Inc’s Founder/CTO, Hiroyasu Hasegawa “As a result, productivity gains along with design reuse will accelerate.  Furthermore, the style guide will enable novice and beginning level design engineers to easily become productive in SystemC based design.  With plentiful free examples and code samples, learning SystemC will be much more streamlined.”

“We have observed a large number of Japanese customers achieve dramatic productivity gains by successfully adopting SystemC-based design,” said Brett Cline vice president of marketing and sales at Forte Design Systems.  “HD Lab’s Design Style Guide will allow companies around the world to leverage this combined experience and quickly adopt SystemC design and synthesis to shorten their overall design cycle.”

Takeshi Hasegawa, Chairing JEITA EDA Technical Committee’s SystemC Working Group commented, “Unlike RTL synthesis, there are no standard coding style for SystemC synthesis.  There were lots of trial-and-error types of approaches.  We are pleased to see that JEITA’s working group’s input has been implemented by HD Lab in this guidebook.”  Hasegawa is also director of ESL & Verification Department at Fujitsu Ltd., further stated “Since key elements of design environment building and know-how for design are organized and available in the design style guide, cost savings to a design team is tremendous.  We expect this new methodology to be the key productivity differentiator.”

Pricing and availability:

The Design Style Guide will be available in Japan from July 31, 2007.  A single corporate license will be 4 million yen per set (approximately $33,000).  

About HD Lab, Inc.

HD Lab, Inc. was founded in 1996 as a professional solution provider for large-scale digital system design. Since its inception, the company has focused on the hardware description language and electronic system level aspect of large-scale LSI design. Their services are provided and delivered in various forms including consulting services, training, and publications, to name a few. The company is headquartered in Shin-Yokohama, Japan and serves customers in Japan
http://www.hdlab.co.jp

JEITA - Japan Electronics and Information Technology Industries Association (www.jeita.or.jp)