Co-Design Automation Launches Innovative Product Line to Reshape System Design Methodologies

SAN JOSE, Calif.----May 8, 2000--Co-Design Automation, Inc., an Electronic Design Automation (EDA) software supplier based here, today unveiled a new design and verification product line, initiating a dramatic productivity improvement for system-on-chip (SoC) design methodologies.

The cornerstone of the product is a system simulator called SYSTEMSIM(TM). It utilizes a next-generation architecture to provide orders of magnitude performance improvements while solving complex SoC verification issues, including the mixed simulation of the Verilog hardware description language (HDL), C/C++, SystemC and SUPERLOG. It is complemented by SYSTEMEX(TM), designed to transform abstract system descriptions to HDL code.

``With our world-leading simulation team, including noted Verilog HDL creator Phil Moorby, we have changed the face of verification,'' affirms Simon Davidmann, president and chief executive officer (CEO) at Co-Design. ``Many existing methodologies are built on a foundation of old technologies, strung together with inefficient interfaces. Co-Design's new simulation architecture provides a powerful, evolutionary alternative toward productive SoC design.''

``Since I created the industry standard Verilog-XL simulator, engineers have continuously explored methods to improve verification performance and productivity,'' adds Phil Moorby, Co-Design's chief scientist. ``SYSTEMSIM enables a leap in productivity, while providing the necessary flexibility for SoC devices.'' About SYSTEMSIM

SYSTEMSIM utilizes three advances: the CBlend(TM) technology, a Parallel Instruction Optimization (PIO) architecture and the SUPERLOG(TM) language simulation.

The CBlend technology provides multi-lingual support for C and C++ programming languages, Verilog HDL and the SUPERLOG system design language, without specialized interfaces -- notably, the Verilog Programming Language Interface (PLI) -- transforming interoperability efficiency.

SYSTEMSIM is the first simulator to support the SystemC and Verilog 2000 standards.

``Transmeta's leading-edge design work requires a highly advanced verification environment to fully exercise inter-operating hardware and software,'' says Godfrey D'Souza, director of Advanced Product Development at Transmeta, Inc. ``Based on our evaluation, Co-Design's CBlend technology offers a new level of efficiency and simplification for co-simulating C-based models with HDL descriptions and, coupled with abstract SUPERLOG constructs, has the potential to significantly shorten our development cycle.''

The new PIO architecture enables superior, compiled-code level simulation performance for behavioral and algorithmic models, while maintaining the fast initialization and interactivity associated with interpreted simulation.

The ability to leverage design abstraction is further enhanced through the use of SYSTEMEX, which provides a path to silicon through standard synthesis for concise SUPERLOG constructs, streamlining the input to current EDA software.

``By enabling the efficient representation of complex structures in a manner requiring many fewer lines of code versus traditional approaches, SUPERLOG allows intelligible models and circuits to be produced quickly and easily,'' says Jon Beecroft, principle consultant at Quadrics Supercomputers World Ltd. ``If `right first time' designs are important to you, I would very strongly recommend SUPERLOG and Co-Design's SYSTEMSIM as the language and simulator of first choice.''

These capabilities, combined with SUPERLOG language simulation, enable multiple advantages for SoC methodologies. Examples include: the ability to produce accurate, concise design descriptions; leverage SUPERLOG- and C-based functional tests; refine software or architectural descriptions against HDL models; and compare SystemC models with legacy designs. All can be performed within the single simulation kernel.

Utilizing architectural advantages of CBlend and PIO, SYSTEMSIM provides high-performance, interactive simulation of Verilog, Verilog2000, C/C++, SUPERLOG and SystemC. The simulator is equipped with SYSTEMVIEW, a graphical debug environment extended for C and SUPERLOG models, as well as standard features found in most HDL simulators.

Support for VHDL will be added within the second half of 2000.

About SYSTEMEX

SYSTEMEX extracts Verilog HDL code from SUPERLOG descriptions for hardware implementation using industry-standard synthesis. This enables an increased level of abstraction for hardware design, resulting in productivity improvements through concise model descriptions and tool performance, improving system to implementation links. SYSTEMEX will be extended to output C code for software development and VHDL for hardware descriptions.

SYSTEMSIM and SYSTEMEX will be continuously demonstrated at the Design Automation Conference (DAC) Monday, June 5, through Wednesday, June 7, at the Los Angeles Convention Center in Los Angeles, in Booth Number 3259.

Pricing and Availability

SYSTEMSIM is shipping now and is priced at $40,000, U.S. list. SYSTEMEX is also available now and is priced at $25,000, U.S. list. Both run on Sun Solaris and Linux.

Contact Dave Kelf, vice president of marketing at Co-Design, for more details. He can be reached via email at davek@co-design.com or at (877) 6 CODESIGN, Ext. 404.

About Co-Design Automation

Co-Design Automation is an EDA company focused on the efficient creation, implementation, and verification of SoC designs. Founded in 1997, it is privately held and funded by investors from within the EDA developer and user communities. The staff includes notable simulation experts Phil Moorby, creator of the Verilog HDL, and Peter Flake, creator of the HILO HDL. In 1999, the company announced the SUPERLOG system design language, now utilized by15 partner companies. Corporate headquarters is in San Jose, Calif. Telephone: (877) 6 CODESIGN. Facsimile: (408) 273-6025. Email: info@co-design.com. On-line information is found at its Web Sites: http://www.co-design.com and http://www.superlog.org.

SYSTEMSIM, SYSTEMEX, CBlend and SUPERLOG are trademarks of Co-Design Automation, Inc. Verilog is a trademark of Cadence Design Systems, Inc. Co-Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

Contact:
     Nanette Collins, 617/437-1822
     nanette@nvc.com
     or
     Co-Design Automation, Inc.
     David Kelf, 617/571-9883
     davek@co-design.com