Certess Certitude Improves Verification Strategy at Juniper Networks
CAMPBELL, Calif. -- August 2, 2007 -- Certess, Inc. today announced that Juniper Networks, the leader in high-performance networking, has adopted Certitude, the first commercial functional qualification software product for companies developing systems on a chip (SoCs) or integrating intellectual property (IP) blocks. Certitude certifies that if a semiconductor chip design had a bug, it would be found.
"We installed Certitude for objective quality assurance for our ASICs," said Kenny Chen, ASIC director at Juniper. "We were using traditional methodologies and they worked to a point, but we were missing something very important, which was an objective measure of the effectiveness of our verification effort. Certitude delivers that, and also enables us to optimize our verification resources and budget."
During the technology evaluation, Juniper was able to very quickly establish both the value and the reliability of Certitude. The initial evaluation took less than one week of engineering resources and delivered the promised results. This gave Juniper the confidence that Certitude would fit into their flow without disrupting very tight schedules.
"Juniper's ASIC methodology and tools are very well respected in the industry," said Certess CEO Michel Courtoy. "They also have a very strong track record of successful ASIC tape-outs. Having Juniper as an early adopter of Certitude reflects very positively on the strength of our product and we are extremely pleased to welcome them as a customer."
Certitude addresses two of the most critical problems associated with the design of semiconductors: first, that the functional verification process consumes more resources than the design process; and second, despite having a set of dedicated tools and methodologies that automate parts of the process and improve verification quality, companies find that functional logic errors are still the largest cause of silicon re-spins.
According to Courtoy, Certitude is already deployed by more than 50 design teams in integrated device manufacturers, fabless semiconductor companies, and system manufacturers throughout the world.
About Certess
Certess, Inc. is the only electronic design automation company providing functional qualification products for companies that create and integrate complex design blocks or intellectual property (IP). The company's technology provides design and verification engineers with an objective way to evaluate and improve the completeness of the verification environment, resulting in a shorter and more predictable process to integrate SoC designs and ensure high quality designs. The company is headquartered in Campbell, CA. For additional information, see www.certess.com.
|
Related News
- Juniper Networks Adopts Jasper Formal Technology to Mitigate Design and Verification Risk
- Certess Certitude Increases Verification Quality at Mellanox Technologies
- Juniper Networks Selects Denali Verification IP for Design and Verification of its Products
- Synopsys and Juniper Networks Invest in New Company to Pursue Fast-Growing Silicon Photonics Market
- Synopsys Chosen by Juniper Networks to Accelerate Development of Photonic ICs for Next-Gen Data Centers
Breaking News
- PUFsecurity Unveils Next-Gen Crypto Coprocessor PUFcc7 Featuring High-speed Performance and TLS 1.3 Support
- VeriSilicon's complete Bluetooth Low Energy IP solution is fully compliant with LE Audio specification
- TASKING and Andes Announce FuSa Compliant Compiler Support for Andes RISC-V ASIL Compliant Automotive IP
- Efabless Launches an "AI Wake Up Call" Open-Source Silicon Design Challenge
- Efinix Rolls Out Line of FPGAs to Accelerate and Adapt Automotive Designs and Applications
Most Popular
- Qualitas Semiconductor and Ambarella Sign Licensing Agreement
- ZeroPoint Technologies Signs Global Customer to Bring Hardware-Accelerated Compression to Hyperscale Data Centers
- Chiplet Interconnect Pioneer Eliyan Closes $60 Million Series B Funding Round, Co-led by Samsung Catalyst Fund and Tiger Global Management to Address Most Pressing Challenge in Development of Generative AI Chips
- Intel and Arm Team Up to Power Startups
- Alphawave Semi and InnoLight Collaborate to Demonstrate Low Latency Linear Pluggable Optics with PCIe 6.0® Subsystem Solution for High-Performance AI Infrastructure at OFC 2024
E-mail This Article | Printer-Friendly Page |