LogicVision Announces Production Release of Memory Built-In Self-Repair and ScanBurst At-Speed Scan Solution Integrated With Mentor Graphic's FastScan and TestKompress
New Release Provides Support for Verilog2001 and a Wide Range of Usability Improvements across the Built-In Self-Test Product Line
SAN JOSE, Calif. -- Aug. 21, 2007 -- LogicVision, Inc., a leading provider of test and yield learning capabilities for the semiconductor industry, today announced major enhancements to its ETCreate(TM) product family. The new release provides comprehensive RTL insertion support for all BIST capabilities, including full support for the Verilog 2001 language, production releases of the company's memory built-in self-repair solution, ETMemory(TM)-Repair, and the company's ScanBurst(TM) at- speed scan solution.
Comprehensive RTL insertion
The ETCreate software provides consistent DFT rule checking for memory, logic and mixed-signal DFT insertion for both RTL and gate level design flows. The latest release is an important milestone, rounding out LogicVision's comprehensive support for the Verilog 2001 (V2K) language constructs, allowing customers to take full advantage of language improvements in V2K without any impact to the RTL insertion flow. The latest release also provides improved design file handling and management capabilities to further streamline the RTL flow.
Memory Built-In Self Repair
LogicVision's memory Built-In Self-Repair solution automatically integrates all of the on-chip capabilities necessary to test, diagnose and permanently repair memories containing redundancy. The solution includes on- chip global fuse management, removing the need for external fuse data storage and greatly simplifying the manufacturing test flow. This solution encompasses all of LogicVision's industry leading hierarchical embedded memory test and diagnostic capabilities and includes LogicVision's automated RTL-level integration and verification flow to ensure minimal impact to the design schedule.
ScanBurst at-speed Scan
ScanBurst is an innovative, new at-speed DFT (Design-for-Test) tool designed specifically to overcome the limitations of traditional at-speed DFT techniques. ScanBurst complements Mentor Graphic's TestKompress(R) and FastScan(TM) ATPG products by providing an environment to allow for easy insertion of scan and clock control structures for accurate at-speed testing, based on LogicVision's patented BurstMode Timing(TM). This enables 3-5X faster ATPG run times and results in 3-5X fewer ATPG patterns. It also enables more accurate at-speed test than traditional double capture techniques. The production release of ScanBurst is available now.
"The adoption of 65 and 45 nanometer process technologies imposes evermore challenges in achieving low DPM (defects per million) levels as well as containing manufacturing test costs," said Farhad Hayat, VP of Marketing at LogicVision. "This latest release of ETCreate further improves the usability of our solutions, allowing design teams to easily adopt the most advanced built-in self-test solution in the industry to meet their quality and test cost goals."
Version 6.0a of the ETCreate product family is in full production and available immediately.
About LogicVision Inc.
LogicVision (Nasdaq: LGVN) provides proprietary technologies for embedded test and yield learning that enable more efficient manufacturing test of complex semiconductors. LogicVision's embedded test solutions allow integrated circuit designers to embed test functionality into a semiconductor design that is used during semiconductor production test and throughout the useful life of the chip. The company's advanced Design for Test (DFT) product line, ETCreate(TM), works together with ETDiagnostic(TM) applications and Yield Insight(TM) to improve profit margins by reducing device field returns and test costs, accelerating silicon bring-up times and shorten both time to market and time to yield. For more information on the company and its products, please visit the LogicVision website at http://www.logicvision.com
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