Monterey Design Systems announces physical design prototyping tool for design closure of ASIC and ASSP designs
MONTEREY DESIGN SYSTEMS ANNOUNCES PHYSICAL DESIGN PROTOTYPING TOOL FOR DESIGN CLOSURE OF ASIC & ASSP DESIGNS
Logic Designers Use Sonar To Define Their Tape-Out Architectures
SUNNYVALE, California - March 27, 2000 - Monterey Design SystemsTM today announced Sonar[tm], a physical design prototyping tool for interactive exploration and optimization of multi-million gate system-on-chip (SoC) designs. With Sonar, logic designers can explore and analyze the impact of their design decisions on die size, clock speed, and chip floorplan at an earlier stage, without waiting for the detailed information obtained after physical place and route. Sonar will enable users to optimize chip speed and size, and make architectural decisions with an accurate analysis of the physical impact, while being confident that the design will be correctly realized in layout with Dolphinâs In One Pass[tm] technology.
Sonar is used as the front-end to the company's flagship product, Dolphinú, The Complete Physical Design System[tm]. As part of a customer's front-end design flow, Sonar is used after synthesis to determine physical implementation difficulties. Users can then interactively refine the netlist for faster layout success with Dolphin. Sonar was developed to provide logic designers with interactive capabilities that will reduce both the design time and cost of complex, deep submicron (0.25 micron and below) designs by improving productivity of their design flows.
"The ability to have a physical prototype of the final layout is like taking blinders off the eyes of front-end designers. They now can make intelligent decisions at the netlist level," stated Jacques Benkoski, president and CEO for Monterey Design Systems. "Because Sonar analyzes the effects of the physical layout data, users can optimize the design for congestion and timing and get to a production tape-out much faster."
Combined with Dolphin, Sonar provides a single environment from netlist to GDSII. The added value of Sonar is that it enables logic designers to finalize their architecture and create a true "hand-off" quality netlist, timing and floorplan for rapid and predictable completion of the physical implementation. Current hand-off methodologies have implied fixing the placement, the timing or both, thereby limiting the flexibility of the final solution and placing unacceptable constraints on the back-end implementation. By analyzing design decisions on die size, physical routing, congestion, cell sizing and timing with a physical prototype, Sonar enables both ASIC vendors and their customers to agree on the sign-off criteria and achieve a tape-out faster.
Sonar accepts a synthesized gate-level netlist, timing and physical constraints and timing libraries as well as a technology file to create a soft floorplan and placement. Sonar then takes the layout process to a point at which timing can be accurately predicted, creating a blueprint of the physical layout. From timing slack graphs and congestion maps, difficult aspects of the design can then be selected and optimized by the user. The optimization can include simple functions such as buffering and cell sizing, as well as more complex technology re-mapping. Designers can place IO cells and mega-cells and pre-route the top-level of clock and power. Users can select objects within the database, set the cost function, and run a given logic optimization algorithm on the specified object.
Fundamental design trade-offs including size, congestion and timing can be interactively optimized to produce a floorplan and netlist that allow Dolphin to achieve design closure. Sonar and Dolphin use a shared database model that allows Sonar to analyze all physical aspects of the placement, routing and optimization of the netlist. Sonar only performs analysis to a level of detail that assures complete design closure when running Dolphin. Because of this, Sonar executes extremely fast without losing any of the detailed information to confidently reach design closure.
Simultaneously with the release of Sonar, Monterey will provide a Web-based version of the product, eSonar. eSonar completes the total design portal solution that Monterey has committed to provide to its customers with the recent announcement of eDolphin. eSonar will bring the collaborative design capability between Monterey's customer and their customers to an even more comprehensive level by extending it to the front-end designers. eSonar will offer the same benefits as eDolphin, such as 24x7 availability, reliability and security.
Pricing and Availability
Both Sonar and eSonar will be available for general release in Q3 Î00. Pricing for Sonar starts at U.S. $105,000 a year for time-based licenses while eSonar users will be able to select from the company's three new business models: global access, design portal and time-based design, that were recently announced with eDolphin.
About Monterey Design Systems
Monterey Design Systems is privately held and backed by leading venture and industrial investors to change the way the world is designing chips. Monterey's Dolphin directly addresses the new and changing design imperatives of multi-million-gate SOCs built on leading-edge semiconductor process technologies. Unlike existing tools, Dolphin's In One Passú architecture with its unique and patented Global Design Technologyú approach solves the complex interdependencies among SoC design factors by simultaneously exploring all aspects of the physical design space. The company is pioneering a Web-based design capability that opens a new and exciting business-to-business paradigm for chip design. A Web-based version of the company's flagship product, eDolphinú is the central component of a total e-services solution that includes software, hardware, network infrastructure, security, information technology and application support. Monterey has introduced revolutionary business models to enable internet age chip designs and benefit customers adopting these solutions. Monterey Design Systems is located at 894 Ross Drive, Sunnyvale, CA 94089-1443, tel: 1.408.747.7370, fax: 1.408.747.7377, http://www.montereydesign.com
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For more information, contact:
Monterey Design Systems
Lee Public Relations