The MathWorks Expands Product Portfolio for Electronic System Verification
NATICK, Mass. -- March 24, 2008 -- The MathWorks today announced it now offers a continuous verification workflow that connects system-level models and algorithms developed in MATLAB and Simulink with digital hardware simulators from the three major EDA companies.
With the availability of EDA Simulator Link DS, which supports cosimulation between MATLAB and Simulink and the Synopsys VCS MX functional verification solution, The MathWorks completes its EDA Simulator Link portfolio, which also includes EDA Simulator Link MQ (for Mentor Graphics’ ModelSim and Questa) and EDA Simulator Link IN (for Cadence Incisive Simulator).
EDA Simulator Link products from The MathWorks offer support for VHDL, Verilog, and mixed-language simulators, enabling engineers to connect MATLAB and Simulink to their choice of hardware description language (HDL) and register transfer level (RTL) simulator for their hardware design and verification tasks. The products also work seamlessly with Simulink HDL Coder from The MathWorks to automate integration of legacy RTL IP with designs developed in MATLAB and Simulink. The EDA Simulator Link products support design teams across FPGA and ASIC markets that are striving to reduce development time, design flaws, and verification costs.
The success of EDA Simulator Link products in improving product quality and cutting verification time has fueled demand for additional interfaces to hardware workflows. As a result, the EDA Simulator Link portfolio has expanded and has prompted EDA vendors to deliver similar tools for analog and mixed-signal simulators such as Synopsys Discovery AMS and Saber, Cadence Virtuoso Multi-Mode Simulation, Cadence PSpice and Cadence Allegro AMS Simulator, and Mentor Graphics ADVance MS (ADMS).
“MathWorks continues its progression from algorithmic development to ESL design and is now addressing the verification portion of the problem,” said Gary Smith, founder and chief analyst at Gary Smith EDA. “In doing so they have moved from a point tool vendor into one offering a large portion of the complete top down design flow.”
“Today’s semiconductor and electronics companies rely on a range of tools to design and verify their products,” said Ken Karnofsky, director of signal processing and communications at The MathWorks. “Now, implementation and verification teams can reuse the algorithm and system-level design and verification work done in MATLAB and Simulink to reduce downstream design and verification time across projects and hardware implementation tools. Such reuse lowers adoption costs by integrating the preferred tools and languages already used throughout the product development process.”
About The MathWorks
The MathWorks is the world’s leading developer of technical computing and Model-Based Design software for engineers and scientists in industry, government, and education. With an extensive product set based on MATLAB and Simulink, The MathWorks provides software and services to solve challenging problems and accelerate innovation in automotive, aerospace, communications, financial services, biotechnology, electronics, instrumentation, process, and other industries.
The MathWorks was founded in 1984 and employs more than 1,800 people worldwide, with headquarters in Natick, Massachusetts. For additional information, visit www.mathworks.com.
|
Related News
- Cadence Delivers 13 New VIP and Expands System VIP Portfolio to Accelerate Automotive, Hyperscale Data Center and Mobile SoC Verification
- Siemens expands industry-leading integrated circuit verification portfolio with acquisition of Avery Design Systems
- Altair Expands Electronic System Design Technology with Acquisition of Concept Engineering
- Cadence Accelerates Industrial, Automotive, Hyperscale Data Center, and Mobile SoC Verification with Expanded VIP and System VIP Portfolio
- Siemens expands industry-leading IC verification portfolio with acquisition of Fractal Technologies
Breaking News
- Omni Design Technologies Joins Intel Foundry Accelerator IP Alliance
- Efabless Announces the Release of the OpenLane 2 Development Platform, Transforming Custom Silicon Design Flows
- TSMC Reports First Quarter EPS of NT$8.70
- Brisbane Silicon publishes DPTx 1.4 IP Core
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
Most Popular
- U.S. Subsidy for TSMC Has AI Chips, Tech Leadership in Sight
- Cadence Unveils Palladium Z3 and Protium X3 Systems to Usher in a New Era of Accelerated Verification, Software Development and Digital Twins
- Zhuhai Chuangfeixin: OTP IP Based on 90nm CMOS Image Sensor Process Technology Successfully Mass Production
- Silvaco Announces Expanded Partnership with Micron Technology
- OPENEDGES Unveils ENLIGHT Pro: A High-Performance NPU IP Quadrupling its Previous Generation's Performance
E-mail This Article | Printer-Friendly Page |