32-Bit RISC-V Embedded Processor and Subsystem, Maps ARM M-0 to M-4. Optimal PPA,
EVE Unleashes DW-FPGA for FPGA Synthesis
Component Library Available for Most Popular FPGA Synthesis Software
SANTA CLARA, Calif. -- May 27, 2008 -- EVE, the leader in hardware/software co-verification, today announced availability of DW-FPGA, a DesignWare® foundation library for use with field programmable gate array (FPGA) synthesis software.
DW-FPGA offers register transfer level (RTL) source code for the most commonly used DesignWare Foundation Library intellectual property (IP) components from Synopsys Inc.
DW-FPGA supports XST® from Xilinx, Quartus® from Altera, Synplicity’s SynplifyPro® and Precision™ from Mentor Graphics Corporation, along with languages Verilog, VHDL and SystemVerilog. It can be used with or without EVE’s ZeBu and for simulation, emulation, prototyping and FPGA designs.
It will be demonstrated, along with EVE’s entire line of hardware/software co-verification solutions, during the 45th Design Automation Conference (DAC) in booth #301 June 9-12 at the Anaheim Convention Center in Anaheim, Calif.
When implementing an application specific integrated circuit (ASIC) design on an FPGA or an FPGA prototyping board, the original ASIC design often uses DesignWare Foundation components not readily available for an FPGA implementation. With DW-FPGA, whenever ASIC-based RTL code references a DesignWare component of the foundation library, the synthesis tool automatically uses the synthesizable definition contained in the provided source code to infer an optimized FPGA description. DW-FPGA includes typical DesignWare functions, including adders, subtracters, multipliers, dividers, cosines and squareroot.
“We welcome the initiative of EVE to bring to market DW-FPGA,” notes Steve Lass, Director of Software Product Marketing at Xilinx. “The combination of Xilinx ISE® Design Suite with EVE’s DW-FPGA library of synthesizable models will allow our customers to quickly implement their ASIC designs onto Xilinx FPGAs.”
Adds Mike Dini, Founder and President of The Dini Group: “Mapping DesignWare functions into FPGAs has long been a cumbersome, expensive, and mysterious undertaking. Worldwide demand for FPGA-based ASIC prototyping, ASIC emulation, and hardware/software co-simulation is increasing exponentially. The demand for cost-effective, third-party solutions for this chore is needed. By offering low-cost support of DesignWare models in FPGAs, EVE solves this irritating issue.”
“EVE is focused on ZeBu, our fast emulation technology,” says Dr. Luc Burgun, EVE’s Chief Executive Officer and President. “However, DW-FPGA is the first EVE offering serving the wider FPGA community with more to come. These products will not be limited to ZeBu users.”
Pricing and Availability
DW-FPGA is priced at $5,000 for a one-year, time-based license provided as a site license. For more information, contact Lauro Rizzatti, General Manager of EVE USA and Vice President of Worldwide Marketing. He can be reached at (+1) (408) 855-3201 or via email at lauro@eve-team.com
About EVE
EVE is the worldwide leader in hardware/software co-verification solutions, including hardware description language (HDL) acceleration and extremely fast emulation.
EVE products significantly shorten the overall verification cycle of complex integrated circuits and electronic systems designs. Its products also work in conjunction with popular Verilog, SystemVerilog, and VHDL-based software simulators from Synopsys, Cadence Design Systems and Mentor Graphics. Website: http://www.eve-team.com
|
Related News
- Microchip Acquires High-Level Synthesis Tool Provider LegUp to Simplify Development of PolarFire FPGA-based Edge Compute Solutions
- Achronix Selects Synopsys' Leading DesignWare IP Solutions to Accelerate Development of High-Performance Data Acceleration FPGA
- Lattice Semiconductor and Synopsys Renew Partnership on FPGA Synthesis Tools
- Menta and Mentor Partner for High-Level Synthesis of Embedded FPGA IP
- Achronix and Mentor Partner to Provide Link Between High-Level Synthesis and FPGA Technology
Breaking News
- Credo at TSMC 2024 North America Technology Symposium
- Cadence Reports First Quarter 2024 Financial Results
- Rambus Advances AI 2.0 with GDDR7 Memory Controller IP
- Faraday Reports First Quarter 2024 Results
- RAAAM Memory Technologies Closes $4M Seed Round to Commercialize Super Cost Effective On-Chip Memory Solutions
Most Popular
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Omni Design Technologies Joins Intel Foundry Accelerator IP Alliance
- Faraday Partners with Arm to Innovate AI-driven Vehicle ASICs
- Semiconductor Capacity Is Up, But Mind the Talent Gap
- Efabless Announces the Release of the OpenLane 2 Development Platform, Transforming Custom Silicon Design Flows
E-mail This Article | Printer-Friendly Page |