Design Reuse
Search EETimes
Silicon IP Verification IP Software IP Wanted IP !!! Free Download IP Analytics (Restricted Access) FPGA Board / Kit Design Services Foundries Main IP/SoC Products Embedded Systems Design Platform / Structured ASIC Foundries FPGA / CPLD Fabless / IDM Deals Legal Business Financial Results People ESL Design Commentary / Analysis Main Silicon IP / SoC Verification IP FPGA / CPLD Embedded Systems Design Platform / Structured ASIC ESL Design ESL Design Standards & Best Practice Structured ASIC Verification IP Main On Cores Embedded Systems EDA Tools IP Cores Tool Demos D&R Partners Research / Market Reports Events Calendar Webcasts / Podcasts Online Bookstore


Comsis introduce the MimoKit-MAX FPGA platform


Related News

Related

Breaking News

Most Popular (Updated Daily)

Paris, France -- June 30, 2008 -- Comsis introduces the MimoKit-MAX platform. The MimoKit-MAX development kit, based on two high-end field-programmable gate arrays (FPGAs), allows the implementation of extremely complex digital processing blocks such as those found in modern multi-antenna Wlan interfaces. The kit has a sufficient gate capacity to host a complete system-on-programmable chip (SoPC), including microcontroller cores and advanced communication peripherals. The MimoKit-MAX is the ideal platform for Wlan-capable SoC prototyping and incorporates a MIMO RF and analog front-end incorporating 2 major sub-blocks:

The analog block consists of 3 IQ codecs which perform the conversions between the digital and analog domains. Each IQ codec contains two matched 80 Msps 10-bit ADCs, and two matched 80 Msps 10-bit DACs. The digital side of the codec’s bank is connected to an FPGA, while the analog side carries the differential signals to the radio transceivers.

The radio block consists of three 2.4GHz/5GHz dual-band radio transceivers. As the MIMO operation requires the same frequency for all the transceivers, they share a local oscillator reference.

Feature set:

  • Two Altera Stratix II devices cumulating more than 3 million ASIC gates equivalent
  • 500 FPGA-FPGA connections, including 64 LVDS pairs
  • 32 Mbits Flash for code or data storage
  • 512 Mbits SDRAM
  • Two Gigabit Ethernet PHY transceivers
  • PCI interface
  • Two USB2 High-speed transceivers, one host and one device
  • Two RS232 level shifters
  • Three AD9861 IQ codecs for baseband conversion
  • MIMO-compatible RF transceivers for configurations up to 3Tx3R
  • Supported by the GRLib/Leon3 IP library from Gaisler Research. This is a comprehensive IP library of a Linux-capable 32-bit embedded processor and peripherals
  • Compatible with Altera Quartus II design software



   

Contact Comsis

Fill out this form for contacting a Comsis representative.

Your Name:
Your E-mail address:
Your Company address:
Your Phone Number:
Write your message:
   

 



E-mail This Article Printer-Friendly Page


<A HREF="http://www.design-reuse.com/banner/exit.php?id=445" target="_top"><IMG SRC="http://www.us.design-reuse.com/adserver/www/images/eureka_static.jpg" WIDTH=125 HEIGHT=125 BORDER=0></A>