Sonics Eliminates Barriers to Multichannel Memory Management Industry Adoption With New Interleaved Multichannel Technology(TM)

IMT(TM) Delivers High Performance with Low Overhead and Operates Transparently to Software and Hardware

MILPITAS, Calif. -- July 1, 2008 -- Sonics Inc., a premier supplier of system-on-chip SMART Interconnect solutions, today announced the availability of Interleaved Multichannel Technology (IMT), a breakthrough in SoC architecture that eliminates the challenges associated with transitioning to multichannel memory management for achieving high memory access performance.

IMT utilizes an innovative memory interleaving methodology as a foundation for managing up to 8 external DRAM channels. User-controlled interleaving addresses the key challenge of adopting multichannel architectures: ensuring that the memory traffic is divided evenly among the channels. IMT also features automatic load balancing, and partial channel configurability. These features enable a single SoC device to support a wider range of external DRAM configurations so they can match application performance levels to a number of markets. IMT is uniquely able to operate transparently to software and hardware by offering highly scalable and flexible performance while isolating the memory configuration details from new and pre-existing software and hardware components, and also by adapting the physical memory channels into an existing application address view.

The shift to high quality, high definition video has placed enormous demands on the efficiency by which an SoC can access external DRAM. Optimizing external DRAM memory performance now dominates SoC architecture development. A trend toward using multichannel memory management has already started within early HQHD SoCs as a result of the inability for conventional single memory channels to achieve HQHD memory bandwidth requirements. Conventional design is breaking down because the natural progression to DDR3 causes an architecture incompatibility between the optimal 64-byte burst sizes required for single-channel DDR3 DRAMs and the underlying processor cache line and primitive data object sizes, such as MPEG, which are normally 32-bytes or less. Data object fetches smaller than the DRAM burst size wastes data cycles, resulting in dramatic drops in external DRAM bandwidth when compared to the original channel bandwidth.

Since bill of material costs are very tight, compensating for these large losses in channel efficiency by adding more DRAMs is not cost effective. Multichannel architectures cost effectively meet HQHD requirements because splitting the access into multiple channels eliminates the wasted cycles and therefore provides full channel performance with a low number or DRAM chips. Multichannel memory management is imperative to increasing memory performance.

Most multichannel implementations today are simple two channel schemes that rely on balancing traffic in the software or with some rudimentary hardware assistance to gain efficiencies. These are point solutions that are tightly coupled to the particular configuration and will need significant re-architecting for derivative products. In addition, there is little predictability or scalability with such approaches. The verification burden to implement multichannel management in hardware introduces high project risks and potentially long design cycles. The availability of IMT eliminates the need for SoC developers to assume these design challenges and their associated risks.

“IMT is designed to decouple the multichannel memory management from the rest of the system, and introduces a proven interleaving methodology that automatically balances the channel loading with high degrees of efficiency and throughput, while managing the splitting and ordering within the scheme to ensure that IMT is transparent to the rest of the system,” said Drew Wingard, CTO, Sonics. “Through an interleaved approach, IMT delivers high performance, predictability and scalability.”

IMT is currently available as part of a new SoncsSX™ SMART Interconnect™ solution. SonicsStudio™ provides configuration and modeling through advanced automation that enables SoC developers to exactly match their specific configuration, but also maintain architecture compatibility with future products. SonicsStudio outputs either SystemC or Verilog-RTL models from the same database, which facilitates rapid transition of the design from architect modeling to chip development.

A new multichannel memory management white paper is also available at www.sonicsinc.com.

About Sonics

Sonics Inc. is a premier supplier of SMART Interconnect solutions that deliver high SoC design predictability and increased design efficiency. Major semiconductor and systems companies including Broadcom, Samsung, Texas Instruments and Toshiba have applied Sonics’ SMART Interconnect solutions in leading products in the wireless, digital multimedia and communications markets. Sonics is a privately-held company funded by Cadence Design Systems, Toshiba Corporation, Samsung Ventures and venture capital firms Investar Capital, TL Ventures, Smart Technology Ventures, and Easton Hunt Capital, among others. For more information, see www.sonicsinc.com.