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Altera and AMPPSM Partner Northwest Logic Announce 266-MHz DDR SDRAM Controller
Altera and AMPPSM Partner Northwest Logic Announce 266-MHz DDR SDRAM Controller
- The DDR SDRAM Controller is Optimized for Altera's APEX(tm) Devices
- New High Performance DDR SDRAM Controller Supports All Standard SDRAM and SGRAM Memory Types
- The DDR SDRAM Controller is Available With Interfaces to a Local Bus, PowerPC, Digital Video, and Altera MegaCore(tm) PCI cores
San Jose, Calif., January 10, 2000* Altera Corporation (NASDAQ: ALTR) and AMPPSM Partner Northwest Logic today announced the availability of a Double-Data Rate (DDR) Synchronous DRAM (SDRAM) Controller with 266-MHz performance. Northwest Logic, developer of the memory controllers, is a member of the Altera Megafunction Partners Program (AMPP), a program created in 1995 to offer programmable logic designers access to "best-in-class" IP cores. Northwest Logic's DDR SDRAM Controller is capable of operating at 266-MHz when implemented into an Altera EP20K400E device. Northwest Logic's DDR SDRAM Controller supports all standard SDRAM memory types and is available with interfaces to a Local Bus, Motorola PowerPC, Digital Video source and Altera MegaCore(tm) PCI cores. In addition, Northwest Logic offers a 133-MHz Single Data Rate SDRAM Controller with the same interface options. The controller also works with all standard Synchronous Graphics RAM (SGRAM).
"This announcement with Northwest Logic highlights the tremendous performance that can be achieved with Altera's PLDs and tools," said Luanne Stechert, Altera's AMPP program manager. "Altera and its AMPP partners are committed to continue delivering IP which enables our customers to develop a highly integrated System-on-a-Programmable Chip(tm) (SOPC) solution as quickly as possible."
"This design was made possible by the very high internal and I/O performance of Altera's APEX(tm) 20KE PLDs and the use of the internal PLL to minimize clock skew. These advantages combined, with the latest Quartus(tm) software, enabled us to very quickly modify our existing SDRAM Controller to support the latest high-speed DDR SDRAMs," according to Allan Douglas, president of Northwest Logic. "The result is a high-performance SDRAM Controller ideal for use in a variety of applications, including embedded computing and digital video."
About Northwest Logic's DDR SDRAM Controller
Northwest Logic has specifically designed its SDRAM Controllers to achieve high performance with minimal routing and pin constraints. The SDRAM Controller provides twice the throughput of other SDRAM Controllers by using sophisticated bank management and access cascading. Using the DDR SDRAM Controller at 266-MHz with a 64-bit memory bus width enables a sustained throughput of 2.1 GBytes/s. It also eliminates SDRAM control complexity by supplying a simple processor-style interface and providing automatic refresh. Northwest Logic's SDRAM Controller supports all standard SDRAM memory types and is available with interfaces to a Local Bus, PowerPC, Video Buffer and Altera PCI Cores. Netlist and source code license options are available. About the EP20K400E Device Northwest Logic's DDR SDRAM Controller has been optimized for the APEX 20KE architecture. The EP20K400E is the first member of the APEX 20KE family of SOPC devices. The EP20K400E device features 16,640 logic elements (LEs) and 212,992 RAM bits in embedded blocks, which can be configured as 1,664 macrocells. The high-performance EP20K400E PLD has 400,000 typical gates (1 million maximum system gates), up to 488 maximum user I/O pins, and operates at 1.8-, 2.5-, and 3.3-volts using MultiVolt(tm) I/O support.
Availability and Pricing
Northwest Logic's new DDR SDRAM Controller megafunction uses approximately 800 logic cells and is available now for $6,995 in encrypted netlist form. The SDRAM Controller is also available in source code (VHDL or Verilog) with a testbench. Customers can evaluate the SDRAM Controller for free prior to licensing as an Altera's OpenCore(tm) Netlist or a ModelSim Compiled Library.
About Northwest Logic
Northwest Logic is a contract engineering design firm located in Beaverton, Oregon. Northwest Logic specializes in high speed, complex programmable logic, board and software development. Northwest Logic also provides high quality system expertise particularly in the areas of digital telecommunications, digital video and embedded computing. Northwest Logic has been a leading Altera Consultants Alliance Program (ACAP(r)) member since the program's inception. More information on Northwest Logic can be obtained at http://www.nwlogic.com.
About AMPP
The Altera Megafunction Partners Program, established in August 1995, was created to bring the advantages of design reuse to users of Altera PLDs. The AMPP program is an alliance between Altera and developers of intellectual property (IP) cores that encourages megafunction development. Altera provides technical information and training to AMPP partners, who create and support IP cores targeted for Altera programmable logic devices. There are 30 partners who offer over 100 megafunctions; customers may automatically request a free evaluation of any of these IP cores by selecting the Altera Alliances link at the Altera web site: http://www.altera.com. About Altera Altera Corporation, The Programmable Solutions Company(tm), was founded in 1983 and is a leading supplier of programmable logic devices and associated logic development software tools. Programmable logic devices are semiconductor chips that can be programmed on-site, using software tools that run on personal computers or engineering workstations. User benefits include ease of use, lower risk, and fast time-to-market. Altera's CMOS-based programmable logic devices address high-speed, high-density and low-power applications in the telecommunications, data communications, computer peripheral, and industrial markets. Altera common stock is traded on the Nasdaq Stock Market under the symbol ALTR. More information on Altera can be obtained on the Internet at http://www.altera.com.
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Altera, The Programmable Solutions Company, AMPP, MegaCore, System-on-a-Programmable-Chip, APEX, MultiVolt, OpenCore, ACAP and specific device designations are trademarks and/or service marks of Altera Corporation in the U.S. and other countries. All other trademarks are the property of their respective holders.
Editor Contacts:
| Rhondalee Rohleder Altera Corporation (408) 544-8296 rrohlede@altera.com | Stephanie Oswold Tsantes & Associates (408) 369-1500 stephanie@tsantes.com | Brian Daellenbach Northwest Logic (503) 533-5800 bdaellenbach@nwlogic.com |
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