Startup QuArc unveils tiny MPEG-2 core

Startup QuArc unveils tiny MPEG-2 core
By Junko Yoshida, EE Times
November 29, 1999 (10:24 a.m. EST)
URL: http://www.eetimes.com/story/OEG19991129S0020

SANTA CLARA Calif. — QuArc Inc., a tiny startup based here, will unveil today what it claims is the fastest and smallest high-definition MPEG-2 video decoder core in the industry.

The core, designed to support 4:2:2 studio-quality MPEG-2 video at a sustained input rate of 300 Mbits/second, is also capable of decoding multiple streams (as many as eight) of DVD or standard-definition video.

The secret ingredient is the core's unique data-driven processing architecture, said Sorin Cismas, president and chief executive officer of the four-person company. Under the patent-pending architecture, each block, embedded with a very small memory, can autonomously operate as an object such as an inverse quantizer, motion vector or motion compensation unit without intervention by an external microcontroller, he said.

The new architecture is depicted by its creators as an attempt to solve one of the tough issues surrounding chip designs based on int ellectual-property (IP) cores: how to efficiently interconnect different cores without facing a huge memory contention dilemma. In a shared-memory system, the QuArc core "is designed to distribute worst-case peak processing loads over more cycles, requiring fewer gates and less power," said Ron Richter, vice president of sales and marketing.

QuArc aims to provide customers with a complete hardware design solution for the MPEG-2 video decoder. Thanks to internally developed design tools, the core's Verilog and C-language interconnections can be reused and easily modified, the company said.

Cost-effective solution?

If the core fits as easily as promised into existing graphics controllers or any other blocks inside a DTV receiver chip set, it could help bring more cost-effective high-definition TV silicon solutions more quickly to market. Today, only a handful of chip vendors offer ICs for MPEG-2 Main Profile @ High Level. No high-definition (HD) MPEG-2 video solutions have yet been made a vailable in the form of IP cores to semiconductor companies.

Still, software might be a problem, industry sources said. "The issue will remain how a new core is designed to address both software and hardware problems," said Gary Smith, chief EDA analyst at Dataquest Inc. (San Jose, Calif.).

Founded in January 1998, QuArc is no stranger to either MPEG-2 video technology or IP core designs. President and CEO Cismas was a co-founder of CompCore Multimedia, a fabless chip company that in the early 1990s developed one of the industry's first MPEG-2 video cores. CompCore's cores were licensed to leading chip companies such as Hitachi, NEC and Cirrus Logic before the company was acquired by Zoran Corp. "This is something all of us at QuArc have done before," said Richter.

QuArc, funded by Cismas with no venture-capital money, is currently working with unnamed partners-presumably, large semiconductor makers with their own fabs-to develop silicon based on its design. The target date for a completed chip, which should serve as a proof of concept, is early summer 2000, Richter said. So far, QuArc has finished the design and simulated the final core.

The startup said that with its core, chip makers can implement HD MPEG-2 video functions in 70,000 to 90,000 gates in a 0.18-micron semiconductor process like that of Taiwan Semiconductor Manufacturing Co. The core, which uses 1.6 kbytes of dedicated internal RAM, is designed for extremely high performance, Richter said. "We cut no corners."

The core is capable of handling full 1,920 x 1,080-pixel, 4:2:2 studio-profile HD MPEG-2 video resolution. An HD MPEG-2 video chip based on QuArc's core running at 111 MHz could use the same available bandwidth to process up to eight streams of 720 x 480-resolution video, for such applications as picture-in-picture or simultaneous multiple-channel viewing. When running at a 154-MHz clock rate, the same core could decode one 4:2:0 HD MPEG-2 video stream and one 4:2:0 DVD-resolution video stream-tasks known to be difficult for CPU-based software processing to handle.

Software questions

Even if the QuArc design can solve underlying hardware architecture issues-critical for interconnecting different cores on a chip — "there is still a big issue of software," said Dataquest's Smith. Chip designers "will still need to wrestle with the interconnectivity of embedded-software virtual components." How the QuArc core links with a real-time operating system, a PCI bus and ports to other microprocessors or DSPs is also an issue, he said.

Kishore Manghnani, vice president of marketing at TeraLogic, a leading HD MPEG-2 decoder silicon provider, also raised a software issue. HD processing is only a very small portion of the entire DTV decoder chip functions, he pointed out. Even if semiconductor companies get the HD MPEG-2 video core from QuArc, "without complete software, it's impossible for them to come up with a system-level solu tion," Manghnani said. "The question is, where do you get the rest of the cores [that handle software]?"

QuArc's Richter acknowledged that the startup's primary focus is hardware. "Quite frankly, at this time, our assumption is that we go one level deeper in the system, while chip vendors or system developers work out higher-level software applications. We don't want to lose focus by going after software as well." If necessary, he said, QuArc will pair potential customers with third-party software vendors like MGI Software (Toronto) or Ravisent Technologies (Malvern, Pa.).

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