IKOS Systems Introduces ARES RTL Acceleration System for Fast Functional Verification

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IKOS Systems Introduces ARES RTL Acceleration System for Fast Functional Verification

CUPERTINO, Calif.----Nov. 8, 1999-- IKOS Systems, Inc. (Nasdaq:IKOS), a leading provider of design verification solutions, today announced its newest fast functional verification product, the ARES(TM) RTL Acceleration System.

This innovative product combines new, high performance hardware acceleration with IKOS' unique RTL compiler technology to offer significant performance advantages over software-only or workstation-based RTL verification solutions while at the same time providing the lowest cost of ownership.

Ramon Nunez, president and CEO of IKOS Systems noted, ``Earlier this year, we established our commitment to fast functional verification with the introduction of our Voyager Fast Functional Acceleration (FFX) RTL verification product. The rollout today of ARES represents the latest in a series of planned product releases as part of our strategic deployment of our RTL technology in the market.''

``Complex SOC designs mandate more robust RTL verification solutions than those that have been offered to the marketplace thus far,'' continued Nunez.

``As more of our customers migrate toward very large SOC designs and RTL sign-off, they are finding that the capabilities of stand-alone software or workstation-based RTL verification solutions have been eclipsed by the bigger, more complex designs that are becoming increasingly commonplace.

``IKOS' proven expertise as a leading provider of design verification solutions is enabling us to anticipate and address our customers' rapidly evolving design verification needs.''

Based upon IKOS' proven acceleration technology and the VHDL and Verilog Fast Functional Acceleration FFX RTL verification technology, ARES is a personal RTL accelerator that offers the highest performance RTL capabilities combined with the lowest cost of ownership.

ARES has a capacity of 1.6 million primitives (3 million RTL user gates); yields compile times of 50,000 gates per minute and provides accelerated simulation times at 7-25X over leading RTL simulators. In addition, this fast functional RTL accelerator provides support for industry-standard synthesizable RTL subsets in VHDL or Verilog and does not require separate simulation libraries.

With a base system price of less than $100,000 USD, the cost of ARES translates to $0.06 per primitive or $0.03 per RTL user gate.

Larry Melling, vice president of strategic marketing and business development for IKOS, stated, ``As with our emulation products, the introduction of ARES further demonstrates IKOS' commitment to the marketplace to provide the highest performance, most robust design verification solutions at the lowest cost of ownership possible.

``ARES combines our RTL compiler with our proven acceleration technology and provides connections to either the Voyager FFX VHDL or Gemini FFX Verilog simulation environments to deliver a complete RTL acceleration solution.''

Perry Farazi, director of VLSI Design at Tellabs Operations, Inc., Bolingbrook, Illinois is one of the first users of the IKOS ARES RTL Acceleration System. He explained, ``With designs averaging 1 million gates per design we are finding that our design verification requirements have scaled exponentially.

``Because the market our company serves is typified by high quality and reliability, it is mandatory that we be able to completely verify our designs early on in the system design process. RTL simulation has become the dominant verification challenge in our design flow especially as our design complexity increases.

``ARES provides us with the robust fast functional performance we need at an affordable price so we can readily incorporate it into our design verification environment.''

ARES Product Features

The ARES RTL Accelerator System includes IKOS' Fast Functional Compiler (FFX) technology. The FFX compiler targets ARES high-performance functional accelerator. The software utilizes high performance Verilog and VHDL analyzers combined with an RTL ``compile for verification'' engine.

The fast compiler accepts industry-standard synthesizable subsets of both VHDL and Verilog languages. Incorporating SRAM/ASIC architectures to provide seven processors on a system board, ARES has a base capacity of 1.6 million primitives (3 million RTL user gates) and yields RTL compile times of 50,000 gates per minute. The cost of a base system is $99,900 USD (Japan: 18 million Yen; other world locations: $139,900).

This price equates to $0.06 per primitive or $0.03 per RTL user gate. ARES also offers a capacity upgrade: adding 2M primitives/ 4M gates capacity expansion for $99,900 bringing ARES maximum capacity to 7M gates.

About IKOS

IKOS Systems, Inc. (Nasdaq:IKOS) is a technology leader in high-performance design verification solutions including hardware and software simulation for language-based design, logic emulation for system integration and compatibility verification, and verification services.

The company's mission is to help customers realize their high-complexity electronic systems through innovative design verification solutions. IKOS has a direct sales operation in North America, UK, France, Germany, and Japan, and a distribution network throughout Asia-Pacific and Israel.

The corporate headquarters are at 19050 Pruneridge Ave., Cupertino, Calif., 95014, 408/255-4567. For more information, visit http://www.ikos.com.

Note to Editors: IKOS, ARES, VOYAGER and GEMINI are trademarks of IKOS Systems. All other brand or product names may be trademarks or registered trademarks of their respective companies and should be treated as such.

Contact:
     IKOS Systems, Inc.
     Larry Melling, 408/366-8522
     larry@ikos.com
       or
     Public Relations
     Kella Knack, 650/508-0371
     Kjcomk@cs.com
       or
     Investor Relations
     Alex Wellins, 415/296-7383