MIPS Technologies introduces world's first synthesizable 64-Bit Processor Core

The MIPS64 5Kc processor core is fully compatible with the MIPS64™ architecture. This makes it compatible with existing MIPS-based™ IP, providing a ready upgrade path for developers. The MIPS64 architecture was designed to ensure IP re-use and software compatibility between 32- and 64-bit processor platforms. This standardizes the MIPS RISC processor architecture and enables real-time operating systems, cache control code, start routines, and application code to be developed once, and executed on any MIPS32™/MIPS64™ compliant processor. The MIPS64 5Kc processor core is a fully static design and includes several power saving modes which bring power consumption down to 1 mW/MHz when using a 0.15 micron CMOS process technology.

"This is a first for our industry," says John Bourgoin, CEO of MIPS Technologies, Inc. "Now chip designers for set-top boxes, handheld computers, Internet appliances, network systems and mobile communication devices have access to a high-bandwidth, high-performance 64-bit drop-in core. This new MIPS® processor core simplifies the integration of 64-bit performance into low cost SOC solutions. Now IC developers can choose to use 64-bit technology without paying a penalty in die size or power consumption."

64-bit resources provide more performance compared to 32-bit processors. Data transfers are twice as fast and 64-bit registers support faster data handling in data-intensive operations. This performance increase greatly affects algorithms that perform regular operations such as encryption and decryption, filtering and data compares. These occur frequently in networking, multimedia, and communications applications.

The MIPS64 5Kc core includes a full 64-bit resource set with 32 general purpose 64-bit registers, four simultaneous execution units, and a six-stage processor pipeline to keep the execution units filled with instructions and data. The design also includes a fast 96-entry TLB-based memory management unit designed for Windows™ CE and other popular real-time operating systems, up to 64 kbyte selectable set-associative caches for both instructions and data, and integrated interfaces to on-chip co-processors.

"In next generation consumer electronics products where high performance and SOC integration is critical, use of highly flexible synthesizable 64 bit processor cores is the emerging trend and companies able to offer this solution will benefit from the growth in this industry." says senior analyst Jay Srivatsa of Dataquest. "According to our 1998 Microprocessor Market Share in Next-Generation Consumer Electronics report published in August 1999, the MIPS processor architecture has nearly 40 percent of the microprocessor market in next-generation products and has lion's share of the microprocessor market in next generation consumer electronics products."

The core design supports flexible, user-configurable implementations. For example, there are four different cache options, alternative memory management units, different EJTAG configurations (for different types of on-board debug), and three different register file implementations. Finally, the co-processor interface supports the integration of on-chip floating-point units, network co-processors, graphics engines or any other user-defined hardware engine. This gives the OEM designer the maximum flexibility to configure the design to meet die size, performance or power consumption parameters. MIPS Technologies' licensees, such as Texas Instruments, will also offer the MIPS64 5Kc as a hard core. This core will be ported and validated for a specific process, providing a complete, easy-to-use core for a broad range of applications.

The new processor design supports 0.18 micron, 0.15 micron and future process technologies and can execute at a worst case clock frequency of 250 MHz (0.18mm) and 300 MHz (0.15mm) clock frequencies. It is available for licensing now and is delivered as a synthesizable RTL file with extensive install, configuration and test tool suites. Support tools include synthesis, scan and ATPG scripts, floorplan design support, pre- and post-layout timing analysis scripts, gate-level simulation and verification suites, bus functional model and cycle-accurate simulation models, functional verification suites, testbench in RTL, implementer's guide and programmer's reference and a test chip specification. MIPS Technologies provides training courses and guidance on software tools.

About MIPS Technologies, Inc.
MIPS Technologies, Inc. is the world's primary architect of embedded 32- and 64-bit RISC processors. The company drives the broadest architectural alliance that is delivering 32- and 64-bit embedded RISC solutions. The company licenses its intellectual property to semiconductor manufacturing companies, ASIC developers, and system OEMs. MIPS Technologies, Inc. and its licensees offer the widest range of robust, scalable processors in standard, custom, semi-custom and application-specific products.

Licensees currently include: Alchemy Microprocessor Design Group; ATI; Broadcom Corporation; Charter Semiconductor; CommQuest (IBM); Integrated Device Technology, Inc. (IDT); LSI Logic Corporation; Macronix; NEC Corporation; NKK Corporation; Philips Semiconductors; Quantum Effect Design, Inc. (QED); Sony Corporation; Synova; Texas Instruments Incorporated and Toshiba Corporation. Numerous companies utilize MIPS-based™ intellectual property. MIPS Technologies, Inc. is based in Mountain View, California, and can be reached at 650-567-5000 or http://www.mips.com

MIPS is a registered trademark of MIPS Technologies, Inc. All other trademarks are the property of their respective companies. All press materials are available on the World Wide Web via: http://www.mips.com.