32-Bit RISC-V Embedded Processor and Subsystem, Maps ARM M-0 to M-4. Optimal PPA,
HDL Design House announces high performance AHB SPI flash memory controller (HIP 3100)
The main features of the HIP 3100 AHB SPI flash memory controller IP core are:
- SPI flash memory controller with AHB slave interface
- Decodes and executes SPI flash memory instructions issued by AHB master
- Provides accurate control signals timing on SPI flash memory interface
- Allows efficient data transfers (read/write) between AHB master and SPI flash memories
- Set of configuration registers to control efficient data transfer between AHB master and SPI flash memories and facilitate software control of the SPI controller
- Offloads AHB master from executing data transfer and controlling the SPI flash memories
- Provides the information about the status and outcome of data transfer to AHB master by interrupt mechanism and status register
- Supports hierarchical organization of SPI flash memories:
- up to 4 SPI flash memory clusters
- up to 4 SPI flash memories in each cluster
- Data transfers can be executed in parallel at SPI memory cluster level providing additional offload level for AHB master
- Dual port Tx/Rx FIFO for each flash memory cluster
The HIP 3100 IP core is available now.
If you are interested in finding out more about the HIP 3100 IP core, please visit www.hdl-dh.com or download the datasheet from the following link: http://www.hdl-dh.com/ipproducts.html
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