Mentor, ARC team up on Celaro emulation

Mentor, ARC team up on Celaro emulation
By Peter Clarke, EE Times
April 15, 1999 (4:29 p.m. EST)
URL: http://www.eetimes.com/story/OEG19990415S0013

LONDON — Mentor Graphics Corp. (Wilsonville, Or.) and ARC Cores Ltd. (ARC) have formed a technology and marketing partnership under which they intend to offer virtual system prototyping of telecommunications and multimedia products.

Based on the combination of Mentor's high-end Celaro hardware emulator and ARC's 32-bit embedded RISC processor, the emulation of ARC-based ASICs and systems will not be available to U.S. engineers, as Celaro is not currently marketed or sold in the United States. In other regions, the companies said they would integrate and support emulation-ready ARC microprocessor cores able to run on Celaro.

None of the emulators from Mentor's Meta Systems unit is currently marketed or sold in the United States, where Quickturn Design Systems Inc. (San Jose, Calif.) filed a patent suit against Mentor and obtained an injunction last year that prevents Mentor from selling Meta Systems' established SimExpress emulator in the U.S. market. When Mentor launched the Celaro emulator in February 1998, the company decided not to the product in the United States.

The ARC core is the second plug-in to Mentor's Celaro emulator and Vivace virtual prototyping environment. In November 1998, Mentor announced that it was developing add-in cards for Celaro for use in situations where silicon is already available for circuit cores around which ASIC teams are designing chips. The first core supported is the ARM7TDMI 32-bit RISC processor from ARM Ltd. (Cambridge, England).

However, as the ARC core is defined at the register transfer level and synthesized to the gate level, users map the ARC processor core into the Celaro emulator's reconfigurable logic together with their overall custom logic.

The Vivace environment allows users to compile designs into the Celaro hardware emulator where a direct connection to the preverified embedded CPU or DSP is made for software debug access. Users can then develop and verify application software against the complete system at megahertz speeds, helping them detect problems that could otherwise go unnoticed until later in the design cycle.

"Putting ARC on to Mentor's Celaro system is not hugely technical, but adding an interface for the ARC Metaware software compiler will allow customers to start software debug straight away," said Stefano Zammattio, market engineering projects manager at ARC (London).

By integrating the 32-bit ARC processor into the Celaro emulator and interfacing it to the Metaware software debugger, Mentor and ARC said a user can verify an ASIC or application-specific standard product and perform hardware/software co-verification at speeds that are orders of magnitude faster than using a conventional approach.

"We have customers developing system-on-chip designs with ARC cores and now they can take advantage of the time and cost savings this solution provides," said Jim Pekarsky, general manager of the Meta Systems division of Mentor Graphics. "The agreement represents another milestone achieved in the Vivace road map for offering customers an expanded scalable solution to address their hardware/software co-verification needs before committing their systems to silicon."

"The strength of the ARC technology is the ease of use combined with outstanding performance," Zammattio said. "This was clearly demonstrated by one of our multimedia customers, who adopted our core and verified their ASSP with the Celaro emulator. The development time of their project shrank by at least four months while the quality of the solution and their confidence in its verification increased significantly."

ARC has also been included in the design of a single-chip MPEG-2 video and audio decoder for set-top-box applications from Fujitsu Microelectronics Inc. The ARC core within the MB87L2250 provides an on-chip CPU to run customer application software such as the electronic-program-guide function.

"We were extremely limited in terms of die size, and did not want to exceed 800-k gates," s aid Albert Dorner, Fujitsu system application engineer for the device. "In consequence, we implemented a very basic ARC core, in fewer than 30-k gates without the cache. Having achieved a very compact processor core, this allowed us to implement a larger cache, for example," he said. Once the hardware team had created a VHDL model, it could also be used to simulate C programs.

"Taken together, the ease with which the core could be configured, and subsequently simulated, greatly improved our time-to-market," Dorner said.