Renesas Technology Halves SiP Design Time with SiP Top-Down Design Environment

New environment enables verification at the initial design stage, significantly reducing SiP design time

London / Munich, 13th July 2009 — Renesas Technology Europe today announced the development of its SiP Top-Down Design Environment to boost efficiency when developing system in package (SiP) products combining multiple chips, such as system on chip (SoC) devices, MCUs, and memories, in a single package. It uses a top-down (predictive) design approach in which key characteristics, such as design quality and heat dispersion, are verified during the initial design stage.

Since an SiP combines multiple chips in a single package, the design of the package substrate configuration and wiring are more complex than is the case for a single-chip SoC device. In addition, signal integrity between the multiple chips and adequate heat dispersion have both become very important because of increased memory speed and capacity, and the accompanying higher power consumption and heat generation density. To achieve quicker SiP development it is therefore critical to ensure signal integrity and to make verification of heat dispersion performance as efficient as possible.

The newly developed SiP Top-Down Design Environment replaces the conventional back annotation (analytical) design methodology, in which these characteristics are analyzed at a late stage of the SiP design process, with a top-down design methodology, in which verification is done in the initial SiP design stage.

In an SiP in which multiple chips are arranged in a stack, the chips and the package substrate are connected by wires. In the past, the analysis of electrical and thermal characteristics was independent of the wire bonding design and package substrate wiring design processes. As a result, it was necessary to update the substrate data manually for each tool used in chip and wiring analysis.

The new design environment uses an integrated design database to provide unified management of design data and easy connections for analysis of electrical or heat dissipation characteristics. Thus, data on chip shapes and positions as well as chip-to-chip connection data can be extracted from the database and connected to the substrate layout tool. In turn, wire bonding and substrate pattern data from the substrate layout tool can be connected to other analysis tools. For enhanced ease of use, a common interface is provided for running the tools and making settings.

Analysis of the electrical characteristics of a large-scale package substrate previously involved division of the area to be analyzed into several sub-areas in order to complete the analysis in a practical amount of time. Since the manner in which the area to be analyzed is divided can affect the accuracy of the analysis, careful consideration had to be given to the division method itself. The circuit simulations also involved complex combinations of analysis conditions, such as SoC drive adjustment. As a result, building the simulation environment and determining the execution results was a very time consuming process, and it was difficult to estimate noise characteristics at the initial design stage.

The new design environment includes an electromagnetic field analysis tool that supports large-scale substrates. This means it is not necessary to divide up the area to be analyzed. In addition, simulation condition setting and result determination for circuit simulations are automated. It is therefore possible to estimate noise at the initial design stage based on the electrical characteristics.

Further, package models for evaluation of heat dispersion characteristics have until now been created manually by referring to the substrate layout data. As a result, the development of package models for heat dispersion evaluation has been time consuming with limited accuracy for the resulting models.

The new design environment extracts from the substrate layout data information on the conductor pattern area share (remaining copper ratio), layer thickness, and materials of the internal SiP package wiring, power plane, etc., the number of via holes between layers, and the shapes and positions of the chips, and it automatically builds an environment for the heat dispersion evaluation package model. Another newly developed function applies the power consumption distribution of the SoC to the thermal analysis model so that the distribution of heat generation within the chips is taken into account. These advances not only increase the accuracy of the models, they make it possible to complete the thermal analysis in a short amount of time.

Renesas Technology plans to expand the application of the SiP Top-Down Design Environment to the development of a broad range of SiP products and will continue to build development solutions that respond to evolving customer requirements.