HDL Design House announces AT25DF161 VITAL behavioral model

Belgrade, Serbia – August 27th 2009 – HDL Design House has announced ATMEL AT25DF161 VITAL behavioral model, 16-Megabit, Serial Flash Memory (SPI). The AT25DF161 is a serial interface flash memory device designed for use in a wide variety of high-volume consumer based applications. The AT25DF161 VITAL behavioral model completely models all aspects of real component behavior/functionality. This includes the checks of all timing relations between input signals (setup/hold, pulse width, etc.) and all delays between inputs and outputs.

AT25DF161 VITAL Behavioral Model Key Features:

• VHDL’93, Verilog and VITAL’2000 compliant models
• Requires VITAL’2000 library for correct compilation
• Timing backannotation by means of an SDF files
• Tested on and compatible with Cadence’s NCSim and Mentor’s ModelSim simulators
• Models are written at a behavioral level and are not synthesizable

Benefits and deliverables:

• Easy to use
• Simplifies system level verification process
• Reduces product development costs
• Speeds time-to-market
• Standard-based for fast, easy integration
• Allows efficient system level simulation/verification
• VHDL and Verilog source code
• Test bench with test cases to test the model

The AT25DF161 VITAL behavioral model can be used along with HDL DH SPI flash memory controller IP core (HIP 3100). The HIP 3100 IP core is an advanced controller for SPI flash memories which off-loads host CPU from direct data transfer control of SPI flash memory. The host CPU can program SPI controller specifying the type of data transfer (SPI instruction, address, data, etc) and SPI controller executes requested transfer. One of supported SPI flash memories is AT25DF161 and both SPI controller (HIP 3100) and AT25DF161 VITAL behavioral model can be used for system level simulations. For more information about HDL DH SPI flash memory controller (HIP 3100) visit http://www.hdl-dh.com/ipproducts.html

VITAL behavioral models are products of close cooperation of HDL Design House (HDLDH) and Free Model Foundry (FMF) company. HDLDH and FMF have developed a thousands of VITAL models. The VITAL model package consists of VHDL and Verilog source code, memory preload files (when appropriate), FTM and SDF files, test cases package file and documentation. The AT25DF161 model and other VITAL models are available for download free of charge from the FMF website (http://www.freemodelfoundry.com).

If you are interested in finding out more about the AT25DF161 VITAL model, please visit www.hdl-dh.com or download model source code from the following link: http://www.freemodelfoundry.com

About HDL Design House:

HDL Design House delivers leading-edge design and verification services and products in numerous areas of SoC and complex FPGA designs. The company develops IP cores and provides complete design and verification services for complex SoC projects. The company also delivers component (VITAL) models for major SoC product developers. Dedicated to fulfilling each customer's unique requirements, HDL Design House has established a reputation as a reliable partner with high-quality products and services, flexible licensing models, competitive pricing and responsible technical support. The company enables customers to concentrate on system-level work and be confident that the various system components have been fully and reliably engineered and tested.
Founded in 2001, HDL Design House has 62 employees in two design centers – in Belgrade and Cuprija (Serbia). The company was awarded ISO 9001:2000 and ISO 27001:2005 certifications in December 2006 and has achieved certifications from Direct Assessment Services (DAS), thereby meeting United Kingdom Accreditation Service (UKAS) regulatory requirements. With ISO 27001:2005 certification, the highest certification standard for information security available, HDL Design House becomes the first company in Serbia to comply with this standard. In 2006 the company was awarded the SME Exporter of the Year by Serbia Investment and Export Promotion Agency (SIEPA).

About FMF:

Founded in 1995, Free Model Foundry is dedicated to promoting standard modeling practices within the electrical engineering community. In particular, we support the use of VHDL, Verilog, and SystemVerilog modeling languages.
One service provided by FMF is to help IC and IP vendors increase the rate of adoption of their products by providing accurate, uniform, functional models to expedite evaluation and selection by designers of electronic systems. Our staff of experienced modeling engineers has developed models simulating over 11,000 parts and takes pride in the ease of use and accuracy of results its products offer.
Free Model Foundry (FMF) believes in free, open source distribution of simulation and analysis models of electronic components. It promotes the development, distribution and sharing of functional simulation models (with timing) for board level components and open source behavioral models for proprietary IP.