ARM Cortex processor technology and physical IP developed in unison to deliver high performance and low-power processing for consumer and enterprise markets
CAMBRIDGE, UK â Sept. 16, 2009 â ARM [(LSE: ARM); (Nasdaq: ARMH)] announced today the development of two Cortexâ¢-A9 MPCoreâ¢ hard macro implementations for the TSMC 40nm-G process, enabling silicon manufacturers to have a rapid and low-risk route to silicon for high-performance, low-power Cortex-A9 processor-based devices. The speed-optimized hard macro implementation will enable devices to operate at frequencies greater than 2GHz.
The dual core hard macro implementations are the result of ARMâs significant investment in advanced physical IP development in unison with processor and fabric IP technology, and leading-edge implementation flows from the EDA industry. Advanced physical IP techniques have enabled critical circuits within the design to be replaced with highly tuned logic cells and memories, increasing performance while lowering overall power consumption.
The Cortex-A9 speed-optimized hard macro implementation will provide system designers with an industry standard ARMÂ® processor incorporating aggressive low-power techniques to further extend ARMâs performance leadership into high-margin consumer and enterprise devices within the power envelope necessary for compact, high-density and thermally constrained environments. This hard macro implementation operates in excess of 2GHz when selected from typical silicon and represents an ideal solution for high-margin performance-oriented applications.
In many thermally constrained applications such as set-top boxes, DTVs, printers and other feature-rich consumer and high-density enterprise applications, energy efficiency is of paramount importance. The Cortex-A9 power-optimized hard macro implementation delivers its peak performance of 4000 DMIPS while consuming less than 250mW per CPU when selected from typical silicon.
The hard macro implementations include ARM AMBAÂ®-compliant high performance system components to maximize data traffic speed and minimize power consumption and silicon area. Each Cortex-A9 hard macro implementation also includes the CoreSightâ¢ Program Trace Macrocell (PTM) which provides full visibility into the processorâs instruction flow, enabling the software community to develop code for optimal performance.
âThe Cortex-A9 MPCore processor has already been widely accepted as the processor of choice for high-performance embedded applications across a broad spectrum of demanding consumer and enterprise devices,â said Eric Schorn, VP marketing, Processor Division, ARM. âARMâs parallel development of advanced, optimized physical IP components demonstrates a new level of collaborative differentiation while enabling our Partners to expand their penetration into high margin domains traditionally occupied by proprietary architectures.â
âARMâs long-standing investment in low-power leadership and ability to develop such high-performance devices enables licensees to lower the cost and risk of entering the high-margin markets currently addressed with competing proprietary solutions,â said Will Strauss, principal analyst at Forward Concepts. âWith single-thread performance capable of supporting very intensive workloads, the unprecedented level of power efficiency will enable licensees to introduce compelling new products.â
âARM and TSMC have enjoyed a long standing relationship of collaboration to ensure the development and delivery of best-in-class products optimized for our manufacturing process,â said ST Juang, Sr. Director, Design Infrastructure Marketing Division, TSMC. âThis provides OEMs developing feature-rich consumer and enterprise devices access to TSMCâs manufacturing excellence and the power of ARM processor IPâ
Both ARM dual core Cortex-A9 hard macros will share a common seven-power domain, dual-NEONâ¢ technology configuration supporting SMP (symmetrical multiprocessing) operating systems with up to 8MB of Level2 cache memory and will be delivered with all scripts, vectors and libraries required to integrate the macro directly within any SoC device.
To enable the development of high-efficiency, low risk SoCs using other Cortex-A9 processor configurations, ARM also provides the silicon-proven SoC-level ARM Physical IP platform used to build these hard macros, and a range of AMBA-compliant system development components and tools.
In addition, the ARM Active Assist consulting service, developed in conjunction with the hard macros, enables ARM Partners to efficiently integrate the hardened macro into their SoC design to realize maximum system performance with lowest risk and fastest time-to-market.
The Cortex-A9 hard macros and the corresponding optimized physical IP used to develop the speed-optimized and power-optimized
implementations are available for license today with delivery in the fourth quarter of 2009. ARMâs 40G physical IP platform is also available today at designstart.arm.com.
ARM designs the technology that lies at the heart of advanced digital products, from wireless, networking and consumer entertainment solutions to imaging, automotive, security and storage devices. ARMâs comprehensive product offering includes 32-bit RISC microprocessors, graphics processors, video engines, enabling software, cell libraries, embedded memories, high-speed connectivity products, peripherals and development tools. Combined with comprehensive design services, training, support and maintenance, and the companyâs broad Partner community, they provide a total system solution that offers a fast, reliable path to market for leading electronics companies. More information on ARM is available at http://www.arm.com.