Faraday SATA 3G PHY & controller First to Achieve Compliance in UMC's 90nm Process Technology

Hsinchu, Taiwan -- September 17, 2009 -- Faraday Technology Corporation (TAIEX: 3035) today announced that their SATA 3G solution is the first to pass SATA-IO compliance test in UMC's 90 nanometer process technology, and becomes the 2nd IP provider in the world to have IP in SATA-IO's Building Block Listing. Meeting compliance requirements helps to ensure interoperability and reduce time-to-market of customers' solutions.

The SATA interface has become the defacto standard for storage applications and been used by 98% of worldwide internal disk drives in 2008. Passing compliance had not been an important requirement yet when SATA 3G was first announced several years ago, which was considered to be overly conservative. However, as board noise level rises with the ever increasing system clocks and interface bandwidth, the electrical quality of SATA signals degrades significantly. Moreover, the SSN (Simultaneous Switching Noise) caused by the highly parallel data bus of SSD flash interfaces eats away the already reduced timing margins. Therefore, passing the compliance has become an essential requirement for ensuring interoperability.

"As a leading provider of IPs and ASIC design services, we are committed to providing solutions that will help bring success to our customers," said Steve Wang, Chief Strategy Officer of Faraday. "For the next two years, 90nm will be the sweet spot process for consumer storage applications such as SSD and PC peripherals. With 90nm standard-compliant PCIe-Gen II and SATA 3G available now, and USB 3.0 available by end of this year, Faraday will offer the most competitive and complete ASIC solution to our customers."

SATA-IO compliance requires strict performances of the important electrical parameters, such as tx jitter, tx rise/fall time balance, rx jitter tolerance, and return loss. Some of these parameters have negative impact on one another, making the design even more challenging. Faraday's design team is able to do this through newly-proposed low jitter phase-locked loop (PLL) and modify clock-data recovery (CDR) circuit. This 3Gb/s CDR employs a half-rate architecture with a 3x-oversampling phase detector and complies with the extended SATA jitter tolerance mask.

"Passing the SATA compliance has been an ultimate goal for IP providers for many years," said Y.K. Tseng, AVP in charge of Mixed Mode IP development at Faraday. "Our ability to meet the compliance requirements not only demonstrates Faraday's HSIO design capability, but also shows our commitment to providing robust solutions to ensure interoperability."

Availability

Available SATA product line covers:

SATA 1.5G/3G PHY at 90nm, and 0.13um
SATA Host Controller
SATA Device Controller

About Faraday Technology Corporation

Faraday Technology Corporation is a leading fabless ASIC and silicon IP provider. The company's broad silicon IP portfolio includes Cell Library, Memory Compiler, ARM-compliant CPUs, DDRI/II/III, MPEG4, H.264, USB 2.0/3.0, 10/100 Ethernet, Serial ATA, and PCI Express. With 2008 revenue of US$ 149 million, Faraday is one of the largest fabless ASIC companies in the Asia-Pacific region, and it also has a significant presence in other world-wide markets. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S., Japan, Europe, and China. For more information, please visit : www.faraday-tech.com