Toshiba Adds 64-Bit MIPS-Based Embedded Microprocessor for Cost-Effective, Next-Generation Digital Consumer Designs

SAN JOSE, Calif., Nov. 19 /PRNewswire/ -- Toshiba America Electronic Components, Inc. (TAEC) with its parent company Toshiba Corporation (Toshiba) today announced development of a new 64-bit  MIPS(TM)-based microprocessor (MPU) to enable a new-generation of cost-effective digital consumer products that can benefit from 64-bit processing power and specialized peripherals. Designated the TX4925, the new chip joins the TX4927 in Toshiba's TX49 lineup and scheduled to sample in February 2002 at $25 in 10,000 piece quantities.

"Most digital consumer designs use 32-bit processors today because the market lacked a cost-effective, high-performance 64-bit solution with the right peripheral selection," said Hiroshi Sekiguchi, director, business development, of TAEC's MPU Business Unit. He explained that Toshiba engineers reduced cache size and used 32-bit peripherals to attain the desired level of price-performance. "Now designers can upgrade to 64-bit processing and gain increased bandwidth and power to manage and unify several media formats of images and sounds from wired and wireless systems," he continued. He added that Toshiba engineers built in NAND Flash memory support for storing user profiles and Micron's SyncFlash(R) for faster accessing requirements and essential peripherals such as a PCMCIA interface, PCI controller and AC-Link controller required by many digital consumer applications.

The company believes the TX4925 provides an array of flexible memory configurations unmatched in the industry. Target applications include broadband audio/video, internet appliances, mobile applications and residential security gateways.

New Features

New functions have been added to an already impressive feature set; these include:

• Personal Computer Memory Card International Association (PCMCIA) slots  to interface radio frequency modules in broadband wireless communications
• An improved 32-bit Peripheral Component Interconnect (PCI) controller  that delivers 120 megabytes per second (Mbytes/sec) sustained  throughput (target), 100Mbytes/sec as initiator transaction performance.  It can connect four master devices such as MPEG-2/4   controllers or Ethernet controllers for digital video recorder     functions.
• New flexible support for external memories that include new NAND Flash    memory and Micron's SyncFlash memory Technical Details

Operating at 200 megahertz with a 1.5 volt (V) core and a 3.3V I/O, the Toshiba TX49/H2 microprocessor reduced instruction set computer (RISC) core is an optimized five stage pipeline with a 64-bit data path, based on MIPS architecture. The core incorporates a memory management unit (MMU) that has a 48-double entry translation lookaside buffer with four-way set-associative 16-kilobyte (KB) instruction and data caches for improved performance compared to typical two-way caches. While providing richer functionality than TX4927, the sizes of the instruction and data caches have been reduced by half to 16KB and the data bus width was halved to 32-bits to achieve a lower unit cost. A hardware multiply accumulator (MAC) and single/double-precision floating-point unit (FPU) are also integrated with the core. The instruction set supports MIPS I, II and III instructions plus MIPS IV prefetch, multiply/add and debug instructions.

External to the microprocessor core, the chip's integrated static direct random access memory (SDRAM) controller can handle four channels of registered/non-registered DIMM SDRAM in configurations up to two gigabytes. An external bus controller supports six channels of read only memory (ROM), Flash, SRAM and memory-mapped I/O devices. A PCI bus controller supports up to four external bus masters. It complies with revision 2.2 of the PCI Local Bus Specification with PCI booting. A direct memory access (DMA) controller supports four independent channels. Also included are a two-channel serial input/output (I/O) port and parallel I/O port, serial peripheral interface, high-speed serial concentration highway interface, three-channel timer/counter and 44-bit up counter real time clock, a AC97 and audio link interface and an AC-Link. Also included are two power-down modes and a reduced frequency function that enables the CPU clock frequency to be reduced by a factor of four reducing overall power consumption.

Hardware and Software Development Environment

The TX4925 supports enhanced JTAG (EJTAG), which allows complete boundary-scan access-to-access inside registers and integrated peripherals. EJTAG can be used to provide single-step execution and hardware break points for debugging the processor system.

Development tools that are planned for support include YDC AdvicePLUS(TM) and Macraigor's Raven(TM) real-time emulators and debug systems, debuggers from RedHat (Cygnus), GreenHills, and Macraigor, and C/C++ compilers from Redhat (Cygnus) and Green Hills. Toshiba provides evaluation and PCI backplane boards. Application specific reference models are provided by Toshiba and third-parties. Real-time operating systems that are scheduled to be supported include embedded Linux(TM), Wind Rivers Systems' VxWorks(R)/Tornado(R) II package and ATI Nucleus(TM).

Package

The TX4925 is housed in a 256-pin plastic ball grid array (BGA) package.

Schedule and Pricing

The TX4925 is slated to sample in February 2002 at $25 in 10,000 piece quantities.

About TAEC

TAEC offers the industry's broadest line-up of semiconductor, display and storage solutions for the computing, wireless, networking and digital consumer markets. Combining quality and flexibility with design engineering expertise, TAEC brings advanced next-generation technologies to its OEM customers.

TAEC is an independent operating company owned by Toshiba America Inc., a subsidiary of the $47.9 billion (FY 2000 recorded sales) Toshiba, the second largest semiconductor company worldwide in terms of global sales for the year 2000. Toshiba is a world leader in high-technology products with more than 300 major subsidiaries and affiliates worldwide. For additional company and product information, please visit TAEC's web site at www.chips.toshiba.com.

All trademarks and registered trademarks are the property of their owners.

For further information please contact: Deborah Chalmers of Toshiba America Electronics Components, Inc., +1-408-526-2454, deborah.chalmers@taec.toshiba.com; or Judy Kahn, +1-650-948-8881, judy_kahn2@yahoo.com, for Toshiba America Electronics Components, Inc.
 

SOURCE Toshiba America Electronics Components, Inc.

/CONTACT: Deborah Chalmers of Toshiba America Electronics Components,
Inc., +1-408-526-2454, deborah.chalmers@taec.toshiba.com; or Judy Kahn,
+1-650-948-8881, judy_kahn2@yahoo.com, for Toshiba America Electronics
Components, Inc./

/Web site: http://www.chips.toshiba.com /

/Web site: http://www.toshiba.com/taec /