Agnisys announces support for OVM Register Package in IDesignSpec
Lowell, MA – Jan 29, 2010 – Agnisys, Inc., the leading provider of innovative automation tools for design and verification of high-end IP and SoCs, today announced the immediate availability of IDesignSpec with support for the OVM Register Package. This comes close on heels of the news on the OVM Register Package 1.0 from Mentor Graphics.
With IDesignSpec, users can describe the entire register map right in their document. This “live” document automatically generates classes and structures compliant with OVM Register Package. Other outputs such as RTL, C/C++ headers, IP-XACT etc. are also possible. Customized outputs can be generated using either Tcl API or XSLT. Running in either interactive or batch mode, users can transform existing IP-XACT (1.4 or 1.5) files into OVM register classes.
“Our patent-pending approach removes the drudgery from the engineers’ life! Engineers don’t need to spend countless hours chasing register bits through the design, verification and validation process. Instead, they describe the register map once and for all, in a document, and that is considered “golden”. All files required by downstream processes are generated from that single source. This improves the engineers’ productivity and quality of results. IDesignSpec provides the most thorough and complete set of functionality in register management space,” said Anupam Bakshi, CEO at Agnisys, Inc.
"We are pleased that Agnisys has made available the first automatic generation of OVM 1.0 register package validated to run on the Questa® functional verification platform," said Dennis Brophy, director of strategic business development, Mentor Graphics. "As a highly active member of the Mentor Questa Vanguard Partnership program, Agnisys works with us to improve design and verification productivity."
IDesignSpec is available for Microsoft Word, Sun StarOffice, OpenOffice.org and Adobe FrameMaker*.
Unique customer engagement model
Agnisys has a unique engagement model, in that its support team helps the customer bring their existing register specs into IDesignSpec. It creates Tcl or XSLT scripts to create the exact output that works in the customer’s existing flow. Without spending much time customers are able to evaluate the tool and the improved work flow. Customers are not locked into the Agnisys file format since the files are stored in the native document editor, under complete control of the user.
A variety of licensing models are available including node locked, floating, site and subscription.
About OVM Register Package
Open Verification Methodology is the first open, language-interoperable, verification methodology in the industry. It provides a methodology and accompanying libraries that allow users to create modular, reusable verification environments in which components communicate with each other via standard transaction-level modeling interfaces. The OVM register package provides a simple, easy to use and easy to extend data model and API for modeling registers, address maps and memories. More information can be found at http://OVMWorld.org
About Agnisys
Agnisys is a pioneer in creating EDA products and services with extreme return on innovation. IDesignSpec (Register automation & management) and IVerifySpec (Verification planning & management) tools enable design and verification teams to exponentially improve productivity and QoR.
IDesignSpec and IVerifySpec are trademarks of Agnisys, Inc. All others are property of their respective owners.
* Adobe’s FrameMaker plugin is currently in Beta.
|
Related News
- Agnisys Announces Wacom Selects IDesignSpecâ„¢ to Automate Its IP and Chip Development Flow from Executable Specifications
- Fraunhofer IIS introduces Application Support Package to facilitate JPEG XS Integration
- Agnisys Announces ISO 26262 and IEC 61508 Qualification for Entire IDesignSpec Suite - SoC Specification Automation Flow
- Agnisys Delivers Novel AI Technology and FPGA Support for IP and SoC Specification Automation
- Weebit undertakes capital raising to support accelerated growth; introduces major Israeli institutional investors onto the register
Breaking News
- Omni Design Technologies Joins Intel Foundry Accelerator IP Alliance
- Efabless Announces the Release of the OpenLane 2 Development Platform, Transforming Custom Silicon Design Flows
- TSMC Reports First Quarter EPS of NT$8.70
- Brisbane Silicon publishes DPTx 1.4 IP Core
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
Most Popular
- U.S. Subsidy for TSMC Has AI Chips, Tech Leadership in Sight
- Cadence Unveils Palladium Z3 and Protium X3 Systems to Usher in a New Era of Accelerated Verification, Software Development and Digital Twins
- Zhuhai Chuangfeixin: OTP IP Based on 90nm CMOS Image Sensor Process Technology Successfully Mass Production
- Silvaco Announces Expanded Partnership with Micron Technology
- OPENEDGES Unveils ENLIGHT Pro: A High-Performance NPU IP Quadrupling its Previous Generation's Performance
E-mail This Article | Printer-Friendly Page |