Jasper Releases New Formal Verification Proof Kits For LPDDR1, LPDDR2 and DDR3
MOUNTAIN VIEW, Calif. – Feb. 22, 2010 – Jasper Design Automation, provider of advanced formal technology solutions, today announced the availability of Proof Kits for LPDDR1 and LPDDR2, and DDR3 SDRAM. These Jasper Proof Kits are sets of properties, written in SystemVerilog, related to standard JEDEC interface protocols. Each Proof Kit includes a Formal Testplan providing detailed instructions on verifying DDR designs, plus properties for the protocol that the JasperGold® Verification System can prove against designs employing the standard. LPDDR solutions are experiencing high growth in mobile and embedded markets as demand for the low-power parts surges.
“These new LPDDR and DDR3 Proof Kits both speed verification for these high-demand memories, and ensure conformance with industry standards,” said Lawrence Loh, Jasper Vice President of Worldwide Applications Engineering. “They join our existing Proof Kits for SDR, DDR and DDR2, and we continue to actively follow and support new standards as they emerge.”
Availability
The new DDR Proof Kits are currently available as a chapter within Jasper Formal Testplanner, and provided at no additional charge to current licensees of Formal Testplanner.
|
Related News
- Jasper DFI Formal Verification Proof Kits Now Available
- Jasper Introduces Intelligent Proof Kits For Faster, More Accurate Verification of SoC Interface Protocols
- Jasper Launches Security Path Verification App - Industry's First Formal Solution for Detecting Security Vulnerabilities in SoC Designs
- Jasper and Duolog Partner to Combine SoC Integration with Formal Verification
- Jasper Makes Formal Verification Power-Aware with a New Low Power App for Verification of SOCs with Multiple Power Domains
Breaking News
- Keysight, Synopsys, and Ansys Deliver Radio Frequency Design Migration Flow to TSMC's N6RF+ Process Node
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Leveraging Cryogenics and Photonics for Quantum Computing
- Kalray Joins Arm Total Design, Extending Collaboration with Arm on Accelerated AI Processing
- Credo at TSMC 2024 North America Technology Symposium
Most Popular
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
- Silicon Creations Reaches Milestone of 10 Million Wafers in Production with TSMC
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Analog Bits to Demonstrate Numerous Test Chips Including Portfolio of Power Management and Embedded Clocking and High Accuracy Sensor IP in TSMC N3P Process at TSMC 2024 North America Technology Symposium
- Alphawave Semi: FY 2023 and 2024 YTD Trading Update and Notice of Results
E-mail This Article | Printer-Friendly Page |