Avery Design Systems Announces AMBA AXI and AHB Verification Solution
ANDOVER, Mass. -- February 22, 2010 -- Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced the AMBA-Xactor verification solution supporting the AMBA 3.0 AXI and AMBA 2.0 AHB specifications.
AMBA-Xactor is a complete verification solution consisting of SystemVerilog OVM/VMM compliant master, slave, and interconnect Bus Functional Models (BFM), protocol checkers, constrained random transaction testing, and reference verification frameworks. The AMBA-Xactor allows design and verification engineers to quickly and extensively test the entire functionality of their AMBA compliant designs.
AMBA-Xactor builds on our solid foundation as a leading supplier of PCI Express, USB 2.0/3.0, Serial ATA, and Parallel ATA verification solutions to IP vendors and semiconductor companies, said Chris Browy, vice president of sales and marketing of Avery Design Systems.
- Supports master, slave, and interconnect fabric topologies of all bus widths
- Supports SystemVerilog VMM and OVM
- Transaction class includes comprehensive constraint set for constrained random testing methodologies
- Supports random wait states on address, data, and response channels and programmable response behavior using transaction-level request matching
- Supports transaction and protocol coverage
- Slave supports simple memory and FIFO models
- Supports data interleaving and multiple outstanding requests
- Supports exclusive access and locked transactions
- Master supports read-verify operation
- Supports wide range of callbacks for convenient error injection and scoreboarding checks
- Supports bus monitor and bus transaction tracker file generator
- Works directly with the ARM AMBA 3 Protocol Checker r0p1 release for comprehensive assertion-based verification
About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of simulation-centric formal analysis, robust core-through-chip-level Verification IP for PCI Express, SATA, USB, and AMBA standards, and scalable distributed parallel logic simulation. The company delivers software products to leading edge semiconductor and systems companies worldwide. Avery Design Systems is privately held. The company is a member of the Synopsys SystemVerilog and VMM Catalyst Programs, Mentor Graphics Modelsim Value Added Partnership (VAP) program, ARM Connected Program, and has established numerous Avery Design VIP partner program affiliations with Rambus, GDA Technologies, Snowbush, and CAST. More information about the company may be found at www.avery-design.com.
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