MoSys Launches the GigaChip(TM) Alliance for Serial Chip-to-Chip Communications
MoSys, Altera and NetLogic Microsystems Create Ecosystem in Support of the GigaChip(TM) Interface for High-Speed Networking Systems
SUNNYVALE, Calif., Jul 2é, 2010 -- MoSys, Inc. (NASDAQ: MOSY), a leading provider of differentiated high-density memory and high-speed interface (I/O) intellectual property (IP), today announced the launch of the GigaChip(TM) Alliance, an ecosystem of semiconductor device suppliers in support of the GigaChip(TM) Interface. The founding alliance participants are: MoSys, Altera Corporation and NetLogic Microsystems. The GigaChip Interface is a board-level, open, CEI-11 compatible interface developed to enable highly efficient serial chip-to-chip communications in next generation high-performance networking, computing and storage systems. In February 2010, MoSys announced the GigaChipInterface as a key element of the new Bandwidth Engine family of ICs. Through the GigaChip Alliance, participating companies will collaborate on expanding the GigaChip Interface for high-speed serial chip-to-chip applications and developing industry-wide open interoperability standards and tools to accelerate the adoption of serial chip-to-chip based system designs.
The GigaChip Interface is a short-reach, low-power serial interface, which enables highly efficient, high-bandwidth, low-latency performance not achievable using currently available serial protocols. Similar to the fundamental performance breakthrough achieved by the move to double data rate (DDR) style interfaces in the late '90s, we believe the GigaChip Interface represents the next breakthrough in chip-to-chip communications using differential SerDes technology. A 16-lane GigaChip Interface can replace up to six separate DDR3 parallel interface busses to memory, which represents a bandwidth density performance increase of 4 times, while reducing system power and interface costs by 2 to 3 times. Such bandwidth density increases will be required to realize line cards with aggregate throughput beyond 100G, a necessity in future high end networking systems. The GigaChip Interface has adopted the open CEI-11 electrical transport standard making use of this existing electrical ecosystem in order to shorten time to market for the introduction of next generation system designs. Through the GigaChip Alliance, companies are enabling an entirely new class of low-cost, high-speed, high-performance systems in networking, computing and storage markets.
"As a leading semiconductor provider to the communications market, we welcome the performance and efficiency that the GigaChip Interface will provide our FPGA customers," commented Arun Iyengar, Senior Director, Communications Business Unit of Altera Corporation. "We are pleased to join the GigaChip Alliance so that we can help drive the evolution of serial chip-to-chip communications technologies, and we plan to support the GigaChip Interface in our FPGAs."
"NetLogic is a worldwide leader in intelligent semiconductor solutions that are powering next-generation internet networks," said Chris O'Reilly, Vice President of Marketing at NetLogic Microsystems. "The GigaChip Alliance is helping to address an important system-level need for a high-bandwidth low-latency interface. We are pleased to collaborate with MoSys as a participant in the GigaChip Alliance."
"We couldn't be more pleased to have such prestigious alliance partners supporting the proliferation of the GigaChip Interface into next generation networking systems," stated David DeMaria, Vice President of Business Operations for MoSys. "Our goal is to revolutionize serial chip-to-chip communications with the GigaChip Interface. Towards that end, we are making the GigaChip Interface an open protocol and encouraging widespread use by potential partners and customers. The GigaChip Alliance will facilitate industry-wide adoption and evolution of this protocol."
About GigaChip(TM) Alliance
The GigaChip Alliance is an ecosystem of companies collaborating to promote and further the development of the GigaChip Interface, a board-level high-speed serial chip-to-chip communications interface standard for high-speed networking systems. Developed by MoSys, Inc., the GigaChip Interface is an open, CEI-11 compatible high-bandwidth, low-latency interface for reliable point-to-point communication of fixed-size frames over short distances. For more information, contact MoSys at http://www.mosys.com/contact.php.
Altera programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more about Altera's FPGA, CPLD and ASIC devices at www.altera.com.
About NetLogic Microsystems
NetLogic Microsystems, Inc. (NASDAQ: NETL) is a worldwide leader in high-performance intelligent semiconductor solutions that are powering next-generation Internet networks. NetLogic Microsystems' best-in-class products perform highly differentiated tasks of accelerating complex network traffic to significantly enhance the performance and functionality of advanced 3G/4G mobile wireless infrastructure, data center, enterprise, metro Ethernet, edge and core infrastructure networks. NetLogic Microsystems' market-leading product portfolio includes high-performance multi-core processors, knowledge-based processors, content processors, network search engines, ultra low-power embedded processors and high-speed 10/40/100 Gigabit Ethernet PHY solutions. These products are designed into high-performance systems such as switches, routers, wireless base stations, security appliances, networked storage appliances, service gateways and connected media devices offered by leading original equipment manufacturers (OEMs). NetLogic Microsystems is headquartered in Santa Clara, California, and has offices and design centers throughout North America, Asia and Europe. For more information about products offered by NetLogic Microsystems, call +1-408-454-3000 or visit the NetLogic Microsystems Web site at http://www.netlogicmicro.com.
About MoSys, Inc.
Founded in 1991, MoSys(R) (NASDAQ: MOSY), develops, markets and licenses differentiated embedded memory and high speed parallel and serial interface IP for advanced SoC designs. MoSys' patented 1T-SRAM(R) and 1T-Flash(R) memory technologies offer a combination of high density, low power consumption, high speed and low cost advantages that are unmatched by other available memory technologies for a variety of networking, computing, storage and consumer/graphics applications. MoSys' silicon-proven interface IP portfolio includes DDR3 PHYs, as well as SerDes IP that support data rates from 1 Gigabit per second (Gbps) to 11 Gbps, across a wide range of standards, including PCI Express, XAUI, SATA and 10G KR. MoSys IP has been production-proven in more than 325 million devices. MoSys is headquartered in Sunnyvale, California. More information is available on MoSys' website at http://www.mosys.com.
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