1-112Gbps Medium Reach (MR) and Very Short Reach (VSR) SerDes
Mentor moves tools toward 16-nanometer
Ron Wilson, EETimes
8/23/2010 3:51 PM EDT
A conversation last Friday (Aug. 20) with Joseph Sawicki, vice president and general manager of the Mentor Graphics Corp.'s Design to Silicon Division, provided a snapshot of the conundra facing foundries and EDA vendors as they approach sub-20-nm process geometries. The landscape is filled with uncertainties, Sawicki warned, but there is no time left to wait for resolution.
"We saw our first 16-nm test chips go out a couple of months ago," Sawicki said in an interview Friday (Aug. 20). "There is design work going on now at that node—so far, though, it is mostly intellectual-property development."
E-mail This Article | Printer-Friendly Page |
|
Related News
- TSMC Certifies Cadence Innovus Implementation System on 16-nanometer FinFET Plus Process
- TSMC Certifies Synopsys Design Tools for 16-nm FinFET Plus Production and for 10-nm Early Design Starts
- Synopsys Tools Achieve TSMC Certification for 16-nm FinFET+ Process and Entered 10-nm FinFET Collaboration
- Mentor Graphics Design and Verification Tools Certified for TSMC 16nm FinFET Production
- Accellera's Security Annotation for Electronic Design Integration Standard 1.0 Moves Toward IEEE Standardization
Breaking News
- Keysight, Synopsys, and Ansys Deliver Radio Frequency Design Migration Flow to TSMC's N6RF+ Process Node
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Leveraging Cryogenics and Photonics for Quantum Computing
- Kalray Joins Arm Total Design, Extending Collaboration with Arm on Accelerated AI Processing
- Credo at TSMC 2024 North America Technology Symposium
Most Popular
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
- Silicon Creations Reaches Milestone of 10 Million Wafers in Production with TSMC
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Analog Bits to Demonstrate Numerous Test Chips Including Portfolio of Power Management and Embedded Clocking and High Accuracy Sensor IP in TSMC N3P Process at TSMC 2024 North America Technology Symposium
- Alphawave Semi: FY 2023 and 2024 YTD Trading Update and Notice of Results