Lattice Announces Serial RapidIO 2.1 AMC Evaluation Platform
Lowest Cost, Lowest Power Programmable SRIO Solution in the Industry
HILLSBORO, OR, Oct 19, 2010 -- Lattice Semiconductor Corporation today announced the availability of a fully integrated evaluation and demonstration platform supporting its Serial RapidIO 2.1 endpoint core utilizing the award winning LatticeECP3(TM) FPGA family. The platform, including the hardware and demonstration software, is based on the industry standard Advanced Mezzanine Card (AMC) form factor and offers users the ability to investigate the lowest cost, lowest power programmable Serial RapidIO solution in the industry supporting 1x, 4x and the new 2x lane configurations at data rates up to 3.125Gbps.
The LatticeECP3 AMC evaluation platform allows designers to investigate and experiment with the features of the LatticeECP3 SERDES and SRIO core in an AMC environment. The board has a single AMC module card edge interface, allowing demonstration of AMC Fat Pipes, and provides a common options interface and a Vita 57.1 FPGA Mezzanine Card (FMC) expansion connector. The AMC board provides a front-panel Small Form Factor Pluggable (SFP) cage and an RJ45 network interface for 10/100/1000 Ethernet connectivity. The AMC platform is additionally populated with DDR2 and Flash memories to support an on-chip soft processor.
This is a fully integrated platform, with the SRIO hardware and associated demonstration software providing the user the ability to exercise the core out of the box operating at 4x2.5Gbps. The evaluation package comes with the AMC board, associated cables and an AMC interface card to support both loopback and interoperation with other AMC designs. The demonstration software is fully contained within a SoC environment that also includes the LatticeMico32(TM) 32-bit soft processor core, and provides a console user interface via a USB cable connection to a PC, allowing the user to interact with the SRIO core via a menu driven interface.
The software menus provide the ability to configure SRIO parameters, display core status and errors and examine local SRIO configuration registers as well as link partner registers. Also supported are the transfers of various SRIO packet types, such as memory transactions, maintenance read/write transactions and doorbell packets, which act as interrupts to endpoints in a Serial RapidIO system.
About the Serial RapidIO 2.1 IP core The small footprint, Serial RapidIO 2.1 IP endpoint core can be used for processor bridging, control plane interfaces and bridging to legacy interfaces. The core architecture for the Serial RapidIO 2.1 IP core includes the following features:
- Allows for 1x, 2x, 4x lane configurations
- Up to 3.125Gbps
- Implements physical layer, transport layer, maintenance transaction handling and error management extensions
- Provides infrastructure support for external logical layer functions, enabling maximum flexibility
- Provides a choice of how logic layer functions interact with the rest of the system -- SoC bus or packet interfaces
- Supports software implementations of control plane oriented functions such as doorbells and messages
- Backward compatible with the v1.3 specification
For additional information about the Serial RapidIO 2.1 IP core, please visit www.latticesemi.com/products/intellectualproperty/ipcores/srio.cfm.
Pricing and Availability
The Serial RapidIO 2.1 IP core and associated AMC platform are available for immediate customer evaluation and use. For more information about licensing and pricing of the Serial RapidIO 2.1 core and AMC platform, please contact your local Lattice sales office or firstname.lastname@example.org.
About the LatticeECP3 FPGA Family
The LatticeECP3 FPGA family is comprised of five devices that offer standards-compliant multi-protocol 3.2G SERDES, DDR1/2/3 memory interfaces for low cost FPGAs and high performance, cascadable DSP slices that are ideal for high performance RF, baseband and image signal processing. Toggling at 1Gbps, the LatticeECP3 FPGAs also feature fast LVDS I/O as well as embedded memory of up to 6.8 Mbits. Logic density varies from 17K LUTs to 149K LUTs with up to 586 user I/O. The LatticeECP3 FPGA family is ideally suited for deployment in high volume cost- and power-sensitive wireless infrastructure and wireline applications.
About Lattice Semiconductor
Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions. For more information, visit www.latticesemi.com
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