Open-Silicon Secures 20th Interlaken IP License
Interlaken IP Achieves Key ASIC Market Milestone
MILPITAS, Calif. – May 24, 2011: Open-Silicon, Inc., a leading semiconductor design and manufacturing company and founding member of the Interlaken Alliance, announced today it has received its 20th ASIC license for the Open-Silicon Interlaken IP core. In addition, the IP has been taped out in 28nm technology and is now silicon proven at 40nm.
“This achievement comes on the heels of a recent competitive Interlaken IP provider acquisition by an FPGA company. We want to highlight the capability of our Interlaken IP, as well as reassure our current and future ASIC customers that we will continue to provide a high quality core and product support,” said Jason Pecor, senior product manager at Open-Silicon. “Open-Silicon is presently in development of the next generation IP core in our Interlaken roadmap.”
In March 2011, Open-Silicon announced recent updates to the Interlaken IP core, including fully-configurable SerDes lane mapping between the logical and physical SerDes lanes. As Interlaken interfaces are routinely targeting SerDes rates greater than 10Gbps, custom mapping of the logical and physical SerDes lanes provides the flexibility necessary to ease board-level design complexities for very high-speed chip-to-chip serial interfaces.
About the ASIC Interlaken IP Core
Combining the advantages of popular SPI4.2 and XAUI interfaces, the Interlaken protocol builds on the channelization and per channel flow control features of SPI4.2, while reducing the number of chip I/O pins by using high-speed SerDes technology. Open-Silicon’s Interlaken IP can scale from 10Gbps to over 300Gbps of bandwidth through the combination of SerDes speed (3.125Gbps to 12.5Gbps) and a variable number of SerDes lanes (1 to 24). This scalability makes Interlaken ideal for multiple generations of future network switches, routers and storage equipment.
The Interlaken protocol is an integral part of today’s leading edge data networking products, enabling fast, low latency chip-to-chip communication for switching, routing, and deep packet processing applications. Architected to be easily synthesizable into many ASIC technologies, Open-Silicon’s Interlaken IP core is uniquely built to work with off-the-shelf SerDes from leading technology vendors. This support for multiple industry-leading SerDes PHYs allows Open-Silicon’s customers to quickly integrate the core into their technology of choice.
Additional details regarding Open-Silicon’s Interlaken IP can be found at http://www.open-silicon.com/capabilities/ip.
About Open-Silicon, Inc.
Open-Silicon is a leading semiconductor company focused on SoC realization for traditional ASIC, develop-to-spec, and derivative ICs. In support of the industry trend towards collaborative engineering and design-lite, Open-Silicon offers SoC architecture, system design, physical design, low-level software, and high-quality semiconductor manufacturing services with one of the world’s broadest partner ecosystems for IC development. For more information, visit Open-Silicon’s website at www.open-silicon.com or call 408-240-5700.
|
Related News
- Open-Silicon Expands Networking IP Portfolio to Address High-Bandwidth Ethernet Endpoint and Ethernet Transport Applications
- Open-Silicon Unveils Industry's Highest Performance Interlaken Chip-to-Chip Interface IP
- Open-Silicon's Interlaken IP Core Selected for Netronome's Next-Generation Flow Processors
- Open-Silicon Unveils Interlaken IP Core with 600 Gbps Chip-to-Chip Interface Support for Networking, Storage and High-Performance Computing Products
- Open-Silicon's Configurable Interlaken IP Core Delivers High-Performance Chip to Chip Interface for Networking Products at 28nm Process Node
Breaking News
- Cadence Announces Most Comprehensive True Hybrid Cloud Solution to Provide Seamless Data Access and Management
- Dolphin Design expands GoAsic partnership to enhance the semiconductor Industry's Supply Chain
- Cadence Collaborates with MemVerge to Increase Resiliency and Cost-Optimization of Long-Running High-Memory EDA Jobs on AWS Spot Instances
- M31 Successfully Validates 5nm IP Solution to Empower Global AI Applications
- Cadence Unveils Palladium Z3 and Protium X3 Systems to Usher in a New Era of Accelerated Verification, Software Development and Digital Twins
Most Popular
- Rivos Raises More Than $250M Targeting Data Analytics and Generative AI Markets
- Semiconductor Capacity Is Up, But Mind the Talent Gap
- Zhuhai Chuangfeixin: OTP IP Based on 90nm CMOS Image Sensor Process Technology Successfully Mass Production
- CMC Microsystems and AIoT Canada Sign Memorandum of Understanding to support IoT and semiconductor ecosystem growth in Canada
- Microchip Technology Acquires Neuronix AI Labs
E-mail This Article | Printer-Friendly Page |