Asserting trio of standards
Asserting trio of standards
By Richard Goering, EE Times
March 18, 2002 (10:48 a.m. EST)
URL: http://www.eetimes.com/story/OEG20020318S0014
There's good news in the verification world, where a serious effort is under way to develop some standards for assertions. But with three separate efforts taking place in Accellera, it's important to clarify what each one is all about.
First, some definitions. A property is a statement about a characteristic of a design, such as, "an acknowledge always follows a request within two cycles." An assertion allows that property to be directly tested in simulation or formal verification, as opposed to hoping you'll hit it with a random testbench.
Standardizing assertions is important because, as I said in an earlier column, we now have a "Tower of Babel" situation, in which multiple vendors are pushing their own assertion formats and languages. That means assertions have to be rewritten for each tool, and you have to lea rn a new assertion language for each vendor. What's needed is a consistent way of writing assertions across the design flow.
Accellera's Verilog Formal Verification (VFV) committee is taking one step in that direction by trying to formulate a standard formal property language. After eliminating candidates from Intel and Verisity, they are now looking at IBM's Sugar and Motorola's CBV. Note that those are new languages, not extensions to Verilog or VHDL. The eventual standard will allow engineers to describe complex temporal properties, and it will most likely be used by systems engineers, not RTL designers.
A second effort unfolded earlier this month, as Co-Design Automation and Real Intent donated the Superlog Design Assertion Subset (DAS) to Accellera's System Verilog committee. That is an attempt to add an assertion mechanism to Verilog, which currently does not have one. It doesn't require Superlog and will work with any Verilog tool, but not with VHDL.
Then there's the Open Verif ication Library (OVL), a library of open-source assertion primitives created by Verplex Systems. It was originally created for Verilog and now supports VHDL. Anyone can use it now by going to the Web site: www.verificationlib.com.
At this juncture, several things need to happen. First, while a coalition of small vendors is supporting the DAS, there needs to be buy-in from Synopsys, Cadence and Mentor Graphics on all of those standards efforts. Second, users need to declare loud and clear that their vendors are going to have to conform to standards. Third, the formal property language, the DAS, and the OVL all must work together.
Related News
- Intrinsic ID Launches First Hardware Root-of-Trust Solution to Meet Functional Safety Standards for Automotive Market
- intoPIX showcases the new lightweight video compression standards and technologies driving automotive innovation at AutoSens 2023
- Tachyum To Use UCIe Interconnect Standards In Prodigy 2
- VESA Showcases Product Demos Supporting DisplayPort 2.1 and Other High-Performance Video Standards at CES 2023
- intoPIX shows the new lightweight video compression standards and technologies driving automotive at CES 2023
Breaking News
- Credo at TSMC 2024 North America Technology Symposium
- Cadence Reports First Quarter 2024 Financial Results
- Rambus Advances AI 2.0 with GDDR7 Memory Controller IP
- Faraday Reports First Quarter 2024 Results
- RAAAM Memory Technologies Closes $4M Seed Round to Commercialize Super Cost Effective On-Chip Memory Solutions
Most Popular
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Omni Design Technologies Joins Intel Foundry Accelerator IP Alliance
- Faraday Partners with Arm to Innovate AI-driven Vehicle ASICs
- Semiconductor Capacity Is Up, But Mind the Talent Gap
- Efabless Announces the Release of the OpenLane 2 Development Platform, Transforming Custom Silicon Design Flows
E-mail This Article | Printer-Friendly Page |