Fab revamp delays Lattice Semiconductor's FPGA architecture
Fab revamp delays Lattice Semiconductor's FPGA architecture
By Chris Edwards, EE Times UK
March 25, 2002 (1:40 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020322S0001
Lattice Semiconductor has been forced to delay the introduction of its own-design FPGA architecture to the end of the second quarter because of streamlining at one of its foundries. Taiwanese foundry UMC, Lattice's supplier, has ended production at one of its fabs, forcing the chip company to transfer the process and the design for the FPGA to another UMC facility. Although the second fab supports the same process, Lattice is re-qualifying the sub-0.18µm technique, incurring at least a three-month delay. Lattice has launched a separate series of FPGAs produced by the design team that it acquired from Agere Systems late last year. These focus on comms-oriented applications. Lattice plans a more generic family based on an architecture brought in as part of its acquisition of Vantis from AMD in 1998. Stan Kopec, vice-president of marketing for Lattice, says the Vantis architecture "has mutated substantially since then". Last year, UMC said it would streamline production to focus on a smaller number of 12in lines in favour of 8in production. At the start of 2001, the company had six fabs in production on 8in lines, but closed its 8B and 8F sites because of low capacity utilisation. Cyrus Tsui, Lattice's chairman and CEO, said: "The FPGA was slated for introduction at the end of last year. It is scheduled now probably for the end of Q2. Half of that delay is because of the fab shutdown. It is the same process but at a different fab." The Agere parts are being built at another foundry, TSMC, on a 0.16µm process with aluminium wiring and transistors running from 1.5V. Tsui says continuing problems with low-k dielectrics in terms of manufacturability and reliability on copper processes mean there is very little foundry production of true 0.13µm devices. "If you see a lot of announcements on 0.13µm but with a core voltage of 1.5V, you know it is not a true 0.13µm process. Ours is an honest 0.16µm," said Tsui. "It is the sooner the better [for devices to move to] copper, but that will be as soon as the low-k dielectric becomes reliable."
Related News
- Lattice FPGA Brings High-Performance MIPI Bridging to Ambarella's CVflow Architecture for Automotive and Machine Vision Applications
- InterMotion Technology boosts IP verification productivity for Lattice Semiconductor's CrossLink FPGA family using Aldec's Active-HDL
- Lattice Semiconductor's iCE40 FPGA Enables Low Latency and Concurrent Sensor Processing in SteamVR Tracking
- Lattice Semiconductor's ECP5 FPGA Enables Energy-Efficient Embedded Vision Systems at the Edge
- Lattice Semiconductor Announces Industry's First True 90nm Non-volatile FPGA Family
Breaking News
- Credo at TSMC 2024 North America Technology Symposium
- Cadence Reports First Quarter 2024 Financial Results
- Rambus Advances AI 2.0 with GDDR7 Memory Controller IP
- Faraday Reports First Quarter 2024 Results
- RAAAM Memory Technologies Closes $4M Seed Round to Commercialize Super Cost Effective On-Chip Memory Solutions
Most Popular
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Omni Design Technologies Joins Intel Foundry Accelerator IP Alliance
- Faraday Partners with Arm to Innovate AI-driven Vehicle ASICs
- Semiconductor Capacity Is Up, But Mind the Talent Gap
- Efabless Announces the Release of the OpenLane 2 Development Platform, Transforming Custom Silicon Design Flows
E-mail This Article | Printer-Friendly Page |