Jennic Launch 10G Intelligent Physical Layer Framers to Extend Optical Utilization Capacity
SHEFFIELD, UK – April 9, 2002- Jennic announced a range of intellectual property (IP) blocks that can be used to create Intelligent Physical Layer Framers for the STS-192/10G optical networking market, addressing the need to increase the capacity of the existing networks.
The product range currently includes an STS-192 SONET Framer, a Payload Processor and an SPI-4.2 Interface. Although these IP blocks are available individually, to allow customers to use them with either their own or 3rd party IP, they are intended to be used with each other to create products suitable for implementation as complete ASSP devices. Jennic provides a one-stop-shop for customers requiring such devices by providing all the necessary IP, including the high-speed IO cells such as LVDS, and the Mixed Signal and SoC implementation services necessary to take the device through from design to manufacture.
"Our latest products offer customers the opportunity to accelerate their product development schedules and to realise products with major differentiating features over those of their competitors," said Jim Lindop, Jennic's CEO. "Jennic's silicon design services provide the capabilities required to achieve right first time silicon for devices of this speed and complexity."
The STS-192 SONET Framer supports the standard SONET mappings down to 192 STS-1 channels and can be used as either a single STS-192 framer or as four individual STS-48 framers. It performs the full termination and generation of the section, line and path overhead bytes and is compatible with 10Gb Ethernet LAN and WAN applications.
The Payload Processor provides the capability to simultaneously encapsulate and decapsulate multiple channels of data using a variety of different protocols including 10GbE, GFP, PPP and ATM. This capability is of particular use in channelised SONET applications where it is permissible to support different protocols and to allocate different amounts of bandwidth across different channels.
The SPI-4.2 Interface allows the transfer of variable length packets and ATM cells between an OIF SPI-4.2 bus and a packet/cell processing engine such as the Payload Processor. The SPI-4.2 Interface supports up to 256 individual Phy channels and contains an integrated, channelised, FIFO. It supports a number of features that are required when used in channelised SONET applications.
Each IP block is provided with a suite of operating system independent device drivers and an application programmer interface. These provide the necessary software routines to perform initialization and dynamic re-configuration as well as providing the facilities to perform exception handling and error and statistics reporting. This allows the system integrator to easily integrate the device into the end system and to concentrate their effort on the higher-level software without having to worry about the lower level software and how it interacts with the device.
Due to the increase in the volume of data traffic and the drive to maximise the utilisation of the optical infrastructure, there has been a growth in demand for physical layer framing devices that provide additional intelligence, rather than simply the ability to transfer larger volumes of data, faster. The term Intelligent Physical Layer Framer has been coined by Jennic to reflect this requirement.
The driving force behind this has been the network providers who want more intelligence to be embedded into the systems on the edge of the metro networks in order to reduce the volume of traffic on the tributary networks and the processing requirements placed on the switches and routers. Examples of how this is being achieved include the use of Forward Error Correction techniques, to increase the reliability and performance of the existing fibre, the use of Virtual Concatenation to provide more efficient utilisation of the available bandwidth and better support for the transport of data through the provision for GFP.
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