400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
Whatever happened to evolvable hardware?
Peter Clarke, EETimes
7/11/2012 10:55 AM EDT
The free market and many other natural systems are supposedly about the survival of the fittest. The survival of the best companies, the success of the best products, the best processors and ICs, and so on.
But what about a circuit that evolves through thousands of iterations, influenced by feedback, until it is optimized for a particular function?
I remember being excited back in the mid 1990s, reading a description of work by Adrian Thompson of the University of Sussex that made use of a Xilinx FPGA to perform the genetic design of evolvable hardware.
E-mail This Article | Printer-Friendly Page |
Related News
Breaking News
- PUFsecurity Unveils Next-Gen Crypto Coprocessor PUFcc7 Featuring High-speed Performance and TLS 1.3 Support
- SEMIFIVE Starts Mass Production of its 14nm AI Inference SoC Platform based Product
- VeriSilicon's complete Bluetooth Low Energy IP solution is fully compliant with LE Audio specification
- TASKING and Andes Announce FuSa Compliant Compiler Support for Andes RISC-V ASIL Compliant Automotive IP
- Efabless Launches an "AI Wake Up Call" Open-Source Silicon Design Challenge
Most Popular
- Qualitas Semiconductor and Ambarella Sign Licensing Agreement
- ZeroPoint Technologies Signs Global Customer to Bring Hardware-Accelerated Compression to Hyperscale Data Centers
- Chiplet Interconnect Pioneer Eliyan Closes $60 Million Series B Funding Round, Co-led by Samsung Catalyst Fund and Tiger Global Management to Address Most Pressing Challenge in Development of Generative AI Chips
- Intel and Arm Team Up to Power Startups
- Alphawave Semi and InnoLight Collaborate to Demonstrate Low Latency Linear Pluggable Optics with PCIe 6.0® Subsystem Solution for High-Performance AI Infrastructure at OFC 2024