Parthus Technologies Announces a Breakthrough in PLL IP Delivery, Putting Design of Custom Clock Synthesis Cores in the Hands of Digital Designers

PLLXpert delivers robust, silicon-proven PLL IP, designed and delivered online in real-time

Dublin, Ireland - April 23, 2002 - Parthus Technologies (Nasdaq: PRTH, LSE: PRH), a leading provider of semiconductor platform-level intellectual property (IP), today announces the launch of a significant new technology approach, PLLXpert Online, for the real-time design and delivery of Clock Synthesis and PLL IP.

Clock Synthesizers, often referred to as Phase Lock Loops (PLLs) are a core technology used in all digital and mixed signal integrated circuits (ICs). Notwithstanding the increased importance of PLLs, they remain one of the most challenging technology blocks to develop and continue to impose considerable risk on the successful deployment of IC products.

To overcome the challenges PLLXpert™, an online PLL generation engine, enables the design of risk-free, silicon-proven PLLs in minutes - shortening the typical development time by months. Designers access the PLLXpert engine over the web at www.pllxpert.com. Through PLLXpert's user interface, the designer simply selects the target process, the reference frequency and the output clocks. No prior training, in-depth PLL design knowledge or additional EDA tools are required. Instant access via www.pllxpert.com to personalised datasheets, verilog models, and the necessary files for logic synthesis and place and route, makes support for the design straightforward. With these outputs, the designer can fully validate the PLL or continue to refine and optimise the PLL to their evolving system requirements. Only when the designer is fully satisfied with the PLL design do they need to pay for delivery of the IP (GDSII file), which again is achieved directly by the user through PLLXpert.com.

"PLLs become increasingly important as embedded microprocessor clock frequencies rise and need to be matched to operating frequencies of other on-chip cores and to external memory. Using its intellectual property, Parthus delivers a web-based environment that, with the right kind of support, will help designers of PLLs for systems-on-chip," said Max Baron, Principal Analyst with Cahners-In-Stat.

The successful delivery of low risk, high performance PLLs draws on the expertise of a team in Parthus of guru specialists with many years of experience. In addition to PLLXpert enabling unrivalled time-to-market advantage, the PLLs generated have industry leading jitter performance. For example a 650MHz PLL targeted at a standard 0.18um foundry process will have a typical jitter sigma of less than 5ps.

"Parthus Clock Synthesis IP Cores (PLL's) have been integrated into a number of our high performance Serial Communication ICs which are currently in production" said Dave Handorff of the Interface Division of National Semiconductor. He went on to say "These devices place extremely demanding requirements on the specification of the PLL IP Core. The Parthus IP has been designed specifically for low jitter and offers the performance that is required for error free data transmission and reception over coaxial cable. In selecting our IP providers we place a high emphasis on those suppliers who can demonstrate a track record of delivering silicon proven IP. Parthus record in this regard has again been demonstrated in a number of devices fabricated across two technology generations which are now successfully in production and shipping in volume."

"PLLXpert Online allows the design engineer to generate state-of-the-art PLL IP Cores in minutes," said Kieran Flynn, PLLXpert Business Manager at Parthus. "With our breakthrough PLLXpert, the designer never has to wait for a PLL to be designed and delivered. Once online, they specify and receive the design as required. That flexibility combined with industry leading jitter performance makes PLLXpert Online a leap forward in IP delivery."

PLLXpert Online is being launched with support for a number of Merchant Foundry and Proprietary Processes:

Foundry processes: PLLs targeted at the TSMC 0.18um and UMC 0.18um processes are currently available online. Further PLL IP Cores targeted at the TSMC 0.13um and TSMC 0.25um will be available online soon. Prior to launch, each new process is verified using a standard test chip containing multiple PLL instantiations, which are designed to exercise the extremes of the design range.

Additional Process Options: PLLXpert is highly flexible and can be ported to a Semiconductor company's own process, enabling both in-house designers and customers to benefit from the risk free, fast time to market offered by PLLXpert Online. Designers using these processes log on to a private users area and design their PLLs on the pre-verified processes.

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This document may contain "forward looking statements''. Any "forward looking statements'' in this document are subject to certain risks and uncertainties that could cause actual results to differ materially from those stated. Any statements that are not statements of historical fact (including, without limitation, statements to the effect that the company or its management "believes,'' "expects,'' "anticipates,'' "plans'' and similar expressions) should be considered forward-looking statements. Important factors that could cause actual results to differ from those indicated by such forward-looking statements include uncertainties relating to the ability of management to complete the planned merger with Ceva, Inc. and to successfully integrate the operations of the two companies, uncertainties relating to the acceptance of semiconductor intellectual property offerings, expansion of our business, quarterly variations in results, and other uncertainties that are discussed in our 2000 Annual Report on Form 20-F which is on file with the SEC since June 26, 2001.