Virage Logic's Shared memory System Increases SoC performance

FREMONT, CA - April  29,  2002, Virage Logic Corp. (Nasdaq: VIRL), a global leader in embedded memory, today introduced a new shared memory system that enables system-on-chip (SoC) designers to increase data throughput by up to 95 percent without increasing die size. With its SRAM-based Custom-TouchTM Area, Speed and Power (ASAP) high-speed multiport register file embedded memory, the company delivers a shared memory system ideal for use in high-speed SoC designs.

Applications driving the use of multiple embedded DSPs, NPUs or graphics chips, such as processors from MIPS or Tensilica, require extremely high throughput without compromising silicon area. Increasingly, SoC designers see the integration of highly parallel or pipelined architecture fast processors on SoCs as critical to next-generation embedded systems. As a result, high performance embedded memory plays an increasingly vital role in achieving the speed target.

"With more and more designers putting multiple processors on-chip, there is a real need for a shared memory system that enables better use of silicon and increased data flow, while ultimately improving the performance of the SoC," said Krishna Balachandran, director of product marketing at Virage Logic. "The ASAP high-speed multiport embedded memory is the industry's first embedded memory commercially available on popular foundries that can instantly configure the number of read and write ports, saving months of design time."

With embedded processors becoming increasingly software re-configurable, SoC designers prefer to have the flexibility to configure the number of read and write ports during the design cycle. Virage Logic's multi-ported register file embedded memory allows for simultaneous writes to different addresses in the same embedded memory. In addition, it simultaneously reads data from any location because it does not compromise the integrity of the data. Because the multi-ported register file embedded memory is re-configurable during SoC design, the designer can perform "what-if" analyses and effectively optimize the system architecture of the chip to achieve the desired area, speed and power targets.

Current solutions for embedded processors use multiple register files with lots of extra logic for simulating multiple read ports, which slows the system's throughput. In order to have multiple write ports, the only solution is to use custom memory instances, adding months to the design cycle. The Virage Logic multi-ported register file increases the speed of processing data or instructions in pipelined or parallel processors by providing simultaneous access to different locations in the same memory.

Regardless of whether the chip architecture is based on parallelism or pipelining, the re-configurable embedded memory (up to a maximum size of 72Kb for one instance) can be optimized for up to a total of six read and write ports for the entire architecture. For an 8Kb instance, the area savings is about 74 percent and the speed increase is about 95 percent using Virage Logic's multi-ported embedded memory, compared to using multiple single port register files with logic.

The memories also feature a user-controlled option that allows for a read and a write operation at the same address during the same clock cycle by using both clock edges, effectively doubling the data rate (DDR). Thus, a 200 MHz design can be enhanced to have an effective throughput of 400 MHz. Moreover, the new memory architecture ensures rapid integration into the design flow through the necessary EDA views and models.

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