Raanana, Israel, November 5, 2012: VLSI Plus, a leading provider of MIPIÂ® CSI2 compliant IP cores, today announced the availability of Alias-DT option, which enables outputting multiple pixels per clock, in all its MIPIÂ® CSI2 Receiver IP cores (the SVR family).
VLSI Plus (www.vlsiplus.com) is a boutique IP house, specializing in digital video and, in particular, in IP cores complying with MIPIÂ® CSI2 and CSI3 Camera Serial Interface standard. VLSI Plus is the first CSI2 IP core vendor to get MIPIÂ® IOL certificate. FPGA versions of its SVR IP cores are extensively used by leading CMOS image sensor vendors for the production floor testing of their sensor modules.
Yoav Lavi, founder and CEO of VLSI Plus said: âWith this feature, the customer can assign an Alias code to any of the CSI2 long-packet data types. For example, the customer can define that data-type = 0x2C (RAW12) will be an alias code for data-type = 0x24 (RGB888). As a result, the SVR IP core will output two RAW12 pixels on its 24 bit Pixel Out bus, per clock.
This new feature allows lower clock frequencies for some of the more popular pixel formats, including RAW12 and all 8 bit formats. For example, a 4-lane RAW8 camera outputting 300M pixel per second will be handled by VLSI Plusâ SVR-CS4 IP core with minimum clock frequency as low as 150MHz.
The new feature is also useful for the second generation SVRPlus-CSI2-I, which can output 2 or 4 pixels per clock without the Alias Data-Type option â using the Alias Data Type in the SVRPlus-CSI2-I further multiplies the number of pixels per clock, typically by a factor of 2 or 3. A SVRPlus-CSI2-I configured for 4 pixels per clock can be programmed to output up to 12 8-bit pixels per clock, if RGB888 is assigned to be an alias code for RAW8
A limited functionality version of the Alias-DT option is also provided with the FPGA versions of VLSI Plusâ SVR IP coresâ