Quad patterning a possibility at 10nm, says TSMC
Rick Merritt, EETimes
10/30/2012 3:31 PM EDT
SANTA CLARA, Calif. – Quad patterning may be needed for 10-nm process technology if extreme ultraviolet (EUV) lithography is not ready in 2015 or so when Taiwan Semiconductor Manufacturing Co. expects to start early production of the technology.
That’s the view expressed by Jack Sun, chief technologist at TSMC, in a brief interview after his keynote at the ARM TechCon here Tuesday (Oct. 30). Sun said quad patterning--four passes through a lithography stepper using four different masks--was one of several options TSMC is exploring as it works on path finding for the process.
E-mail This Article | Printer-Friendly Page |
Related News
- Synopsys' Custom Compiler Certified for TSMC 10-nm and 7-nm FinFET Process Nodes
- Synopsys Successfully Tapes Out Broad IP Portfolio for TSMC 10-nm FinFET Process
- Synopsys Tools Achieve TSMC Certification for 16-nm FinFET+ Process and Entered 10-nm FinFET Collaboration
- TSMC Says 10nm on Track, Countering Reports
- eMemory's NeoFuse IP Verified in TSMC 10nm FinFET Process
Breaking News
- Cadence Reports First Quarter 2024 Financial Results
- Rambus Advances AI 2.0 with GDDR7 Memory Controller IP
- Faraday Reports First Quarter 2024 Results
- RAAAM Memory Technologies Closes $4M Seed Round to Commercialize Super Cost Effective On-Chip Memory Solutions
- Alphawave Semi Audited Results for the Year Ended 31 December 2023
Most Popular
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Omni Design Technologies Joins Intel Foundry Accelerator IP Alliance
- Faraday Partners with Arm to Innovate AI-driven Vehicle ASICs
- Semiconductor Capacity Is Up, But Mind the Talent Gap
- Efabless Announces the Release of the OpenLane 2 Development Platform, Transforming Custom Silicon Design Flows