Grenoble, France December 7, 2012. Dolphin Integration announces that the memory architecture RHEA, achieving leakage as low as 0.84 pA/bit at 90 nm uLL embedded flash process has now passed the pre-silicon assessment criteria (Level 1) of TSMCs stringent IP9000 qualification program.
We are happy to announce that the SpRAM RHEA generator is now available free of charge, for all TSMC 90 nm uLL process users. The RHEA architecture not only provides the best combination of density and leakage, but also features the capability to operate down to 1.0 V ± 10% at the 90 nm uLL process. This is the right SpRAM architecture to meet the challenging needs of MCUs in automotive, consumer and industrial applications, said Elsa BERNARD-MOULIN, Dolphin Integration Marketing Manager for Libraries.
Dolphin Integration plays up the benefits of moving down to a 90 nm uLL process node:
- Storage capacity of more than 800 kbits/mm2
- Access time of 195 MHz for a 4k x 32 memory cutRHEA
- Equivalentleakage at 90 nm uLL versus 180 nm uLL thanks to source biasing implementation and a mix of HVT and SVT MOS, together with dynamic power consumption divided by 3
The SpRAM RHEA Generator is "Foundry Sponsored".
For more information about this product, feel free to download the Presentation Sheet or to contact Dolphins Library Marketing Manager at firstname.lastname@example.org
To request a free access to the FE generator for evaluation purpose or to the BE generator for integration, please click here
About Dolphin Integration
Dolphin Integration is up to their charter as the most adaptive and lasting creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation as well as independence and partnerships with Foundries. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components, such as mixed signal high-resolution converters for audio and measurement applications, Libraries of memories and standard cells, Power management networks, Microcontrollers. The strategy is to follow product launches with evolutions addressing future needs, emphasizing resilience to noise and drastic reductions of power-consumption at SoC level, thanks to their own missing EDA solutions enabling Support Engineering with Application Hardware Modeling as well as early Power and Noise assessment, plus engineering assistance for Risk Control