New GigaOpt “Route-Driven” Optimization Improves Chip Power, Performance and Area for Large, Complex Networking Design
SAN JOSE, Calif., 23 Jan 2013 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced today that Avago Technologies®, a leading supplier of analog interface components, used Cadence® Encounter® Digital Implementation (EDI) System to accelerate the design schedule and boost engineering productivity on a large-scale 28-nanometer networking chip. Avago achieved performance of 1GHz, a 57 percent improvement compared to the previous software. In addition, full-chip implementation turnaround time improved through faster timing closure and fewer design iterations. Cadence is currently collaborating with Avago on its next high-speed networking chip—a 150 million-gate design.
“By working with Cadence, we have boosted productivity for our 28-nanometer designs,” said Frank Ostojic, vice president and general manager, ASIC Products Division at Avago. “The EDI System’s new GigaOpt technology enabled improved runtimes, which is critical to hit the market windows for our large designs.”
The EDI System provides an effective methodology to optimize power, performance, and area for high-performance, giga-scale designs. In addition, integrated “in-design” signoff capabilities in EDI System ensure correlation between timing and power calculations used during implementation and the final calculations produced by signoff engines, reducing iterations between the implementation and signoff stages, resulting in improved productivity for the design team.
GigaOpt technology—introduced earlier this year in EDI System—is a unique technology that integrates physical-aware synthesis technology with physical optimization, enabling faster timing closure and better correlated results. It is a highly scalable optimization technology that leverages multi-threaded processing in leading high-performance processors. In Avago’s latest 28-nanometer design, GigaOpt’s “route-driven” optimization, in which the tool takes into account routing layer considerations earlier in the flow, contributed significantly to the improved quality of results obtained during timing optimization.
“Avago was faced with the challenge of moving a remarkably complex design to market quickly while maintaining the ambitious metrics that ensure high-quality silicon,” said Dr. Chi-Ping Hsu, senior vice president, Research and Development, Silicon Realization Group at Cadence. “The EDI System, with features like the GigaOpt engine, helped Avago meet its power, performance and area requirements for this large-scale project.”
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
About Avago Technologies
Avago Technologies is a leading supplier of analog interface components for wireless, wireline, and industrial applications. By leveraging its core competencies in III-V compound and silicon semiconductor design and processing, the company provides an extensive range of analog, mixed signal and optoelectronics components and subsystems to approximately 40,000 end customers. Backed by strong customer service support, the company's products serve three diverse end markets: wireless communications, wired infrastructure, industrial and automotive electronics. Avago has a global employee presence and heritage of technical innovation dating back 50 years to its Hewlett-Packard roots. Information about Avago is available on the Web at www.avagotech.com.